Method of Measuring Overlay Error and a Device Manufacturing Method

Abstract

The overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.

1 . A method comprising:
 forming a target on a substrate using a lithographic apparatus;   forming a device feature in a chip area on the substrate using the lithographic apparatus;   determining an overlay error of the device feature, wherein the determining the overlay error of the device feature comprises:
 measuring an overlay error of the target using an inspection apparatus, 
 calculating a difference between a measured overlay error of the target and the overlay error of the device feature due to a characteristic of the lithographic apparatus, 
 calculating a difference between the measured overlay error of the target and the overlay error of the device feature due to a difference in position between the target and the device feature on the substrate, and 
 calculating a difference between the measured overlay error of the target and the overlay error of the device feature due to a characteristic of the device feature; and 
   adjusting a parameter of the lithographic apparatus before subsequent processing on a same layer or another layer based on the overlay error of the device feature.   
     
     
         2 . The method of  claim 1 , wherein the characteristic of the lithographic apparatus is an aberration. 
     
     
         3 . The method of  claim 1 , wherein the characteristic of the lithographic apparatus is an illumination mode of the lithographic apparatus. 
     
     
         4 . The method of  claim 1 , wherein the characteristic of the lithographic apparatus is a polarization state of the lithographic apparatus. 
     
     
         5 . The method of  claim 1 , wherein the inspection apparatus is integrated into the lithographic apparatus. 
     
     
         6 . The method of  claim 1 , wherein the target is outside the chip area. 
     
     
         7 . The method of  claim 6 , wherein the target is in a scribelane. 
     
     
         8 . A method comprising:
 forming a target on a substrate using a lithographic apparatus;   forming a device feature in a chip area on the substrate using the lithographic apparatus, the device feature being different than the target;   measuring an overlay error of the target using an inspection apparatus;   modeling an overlay error of the device feature based on a measured overlay error of the target; and   adjusting a parameter of the lithographic apparatus before subsequent processing on a same layer or another layer based on a modeled overlay error of the device feature.   
     
     
         9 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based on data from a database. 
     
     
         10 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based on theoretical data. 
     
     
         11 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based a location of the device feature on the substrate and a location of the target on the substrate. 
     
     
         12 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based a measured aberration of the lithographic apparatus. 
     
     
         13 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based an illumination mode of the lithographic apparatus. 
     
     
         14 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based a polarization state of the lithographic apparatus. 
     
     
         15 . The method of  claim 8 , wherein the modeling the overlay error of the device feature is further based a characteristics of the device feature. 
     
     
         16 . The method of  claim 8 , wherein the modeling the overlay error of the device feature comprises using a model generated by measuring an overlay error of a sample device feature having substantially same characteristics as the device feature. 
     
     
         17 . The method of  claim 8 , wherein the modeling the overlay error of the device feature comprises simulating a relative difference between an overlay error of the device feature and a measured overlay error of the target. 
     
     
         18 . The method of  claim 8 , wherein the inspection apparatus is integrated into the lithographic apparatus. 
     
     
         19 . The method of  claim 8 , wherein the target is outside the chip area. 
     
     
         20 . The method of  claim 19 , wherein the target is in a scribelane.