Method of Forming an Embedded Memory Device

Abstract

The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

What is claimed is: 
     
         1 . A memory structure, the structure comprising:
 a wafer substrate;   a source formed in the wafer substrate;   a drain formed in the wafer substrate; and   a poly stack pattern disposed over the source at one end of the poly stack pattern and over the drain at another end of the poly stack pattern, wherein the poly stack pattern includes a memory gate over the source and a control gate over the drain.   
     
     
         2 . The structure of  claim 1 , wherein the memory gate is separated with the wafer substrate by an interfacial layer deposited over the wafer substrate, a nitride layer deposited over the interfacial layer, and an oxide layer deposited over the nitride layer. 
     
     
         3 . The structure of  claim 2 , wherein the memory gate is formed over the oxide layer. 
     
     
         4 . The structure of  claim 3 , further comprising the memory gate buried inside the oxide layer 
     
     
         5 . The structure of  claim 1 , wherein the control gate is separated with the wafer substrate by the interfacial layer deposited over the wafer substrate, a high-k dielectric layer deposited over the interfacial layer, and a metal nitride layer deposited over the high-k dielectric layer. 
     
     
         6 . The structure of  claim 5 , wherein the control gate is formed over the metal nitride layer. 
     
     
         7 . A device comprising:
 a memory gate region disposed over a semiconductor substrate, the memory gate region including:
 an interfacial layer disposed over the semiconductor substrate in the memory gate region; 
 a memory gate disposed over the interfacial layer; and 
 a spacer disposed along a sidewall of memory gate and disposed between the memory gate and the interfacial layer; 
   a control gate region disposed over the semiconductor substrate, the control gate region including:
 the interfacial layer disposed over the semiconductor substrate in the control gate region; 
 a high-k dielectric layer disposed over the interfacial layer in the control gate region; 
 a metal nitride layer disposed over the high-k dielectric layer; and 
 a control gate disposed over the metal nitride layer. 
   
     
     
         8 . The device of  claim 7 , wherein the memory gate region is free of the metal nitride layer. 
     
     
         9 . The device of  claim 7 , wherein the spacer includes a first material layer and a second material layer,
 wherein the first material layer physically contacts the sidewall of the memory gate and a bottom surface of the memory gate, the bottom surface of the memory gate facing the semiconductor substrate, and   wherein the second material layer extends along the sidewall of the memory gate adjacent the first material layer and under the memory gate adjacent the first material layer, wherein the second material layer physically contacts a top surface of the interfacial layer disposed over the semiconductor substrate in the memory gate region, wherein the top surface of the interfacial layer faces away from the semiconductor substrate.   
     
     
         10 . The device of  claim 9 , wherein the control gate, the metal nitride layer, and the high-k dielectric layer physically contact the second material layer. 
     
     
         11 . The device of  claim 9 , wherein the first material layer includes silicon oxide and the second material layer includes silicon nitride. 
     
     
         12 . The device of  claim 7 , wherein the semiconductor substrate includes a source feature,
 wherein the memory gate is disposed directly over the source feature,   wherein the semiconductor substrate includes a drain feature, and   wherein the control gate is disposed directly over the source feature.   
     
     
         13 . The device of  claim 7 , wherein the interfacial layer extends continuously from the memory gate region to the control gate region. 
     
     
         14 . The device of  claim 7 , wherein the spacer is further disposed over a top surface of the memory gate such that the memory gate is a buried memory gate. 
     
     
         15 . The device of  claim 14 , wherein the spacer includes an oxide material. 
     
     
         16 . A device comprising:
 a memory gate region disposed over a semiconductor substrate, the memory gate region including:
 an interfacial layer disposed over the semiconductor substrate in the memory gate region; 
 a spacer layer having a u-shaped profile defining a recess, the spacer layer disposed directly on the interfacial layer; and 
 a memory gate disposed within the recess; and 
   a control gate region disposed over the semiconductor substrate, the control gate region including:
 the interfacial layer disposed over the semiconductor substrate in the control gate region; 
 a high-k dielectric layer disposed directly on the interfacial layer in the control gate region; 
 a metal nitride layer disposed directly on the high-k dielectric layer; and 
 a control gate disposed directly on the metal nitride layer. 
   
     
     
         17 . The device of  claim 16 , wherein the memory gate has a top surface facing away from the semiconductor substrate,
 wherein the spacer has a top surface facing away from the semiconductor substrate,   wherein the control gate has a top surface facing away from the semiconductor substrate, and   wherein the top surfaces of the memory gate, the spacer, and the control gate are coplanar.   
     
     
         18 . The device of  claim 16 , wherein the memory gate has a top surface facing away from the semiconductor substrate,
 wherein the spacer has a top surface facing away from the semiconductor substrate,   wherein the control gate has a top surface facing away from the semiconductor substrate,   wherein the top surfaces of the spacer and the control gate are coplanar, and   wherein the top surface of the memory gate is not coplanar with the top surfaces of the spacer and the control gate.   
     
     
         19 . The device of  claim 16 , wherein the control gate, the metal nitride layer, and the high-k dielectric layer physically contact the spacer layer. 
     
     
         20 . The device of  claim 16 , wherein the spacer layer is separated from the memory gate by another spacer layer disposed within the recess.