Methods of making compliant semiconductor chip packages

Abstract

A compliant layer is provided over a face of an undiced semiconductor wafer to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in the undiced wafer, each semiconductor chip having a plurality of contacts at its face. The compliant layer has a bottom surface adjacent the chip face, a top surface facing away from the bottom surface, and a sloping surface between the top and bottom surfaces. Bond ribbons of electrically conductive material are formed each extending from a contact of a respective semiconductor chip, along the sloping surface and the top surface of a portion of the compliant layer to a terminal supported by the top surface of the compliant layer. The packages are then separated from one another by dicing the wafer at semiconductor chip boundaries.

1 . (canceled) 
     
     
         2 . A method of making a plurality of semiconductor chip packages comprising:
 forming a compliant layer overlying a face of an undiced semiconductor wafer so as to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in said undiced wafer, each semiconductor chip having a plurality of contacts at said face,   wherein each said portion of said compliant layer has a bottom surface adjacent said face, a flat top surface facing away from the bottom surface, and a sloping surface between said top and bottom surfaces;   then, for each of a plurality of said portions, forming a bond ribbon of electrically conductive material extending from a contact of a respective semiconductor chip, along said sloping surface and said top surface of said portion, and providing a terminal supported by said top surface and electrically coupled with said contact through said bond ribbon; and   separating said packages from one another comprising dicing said wafer at boundaries of said semiconductor chips.   
     
     
         3 . The method as claimed in  claim 2 , wherein said forming said compliant layer comprises simultaneously forming said compliant layer on each said semiconductor chip. 
     
     
         4 . The method as claimed in  claim 3 , wherein said forming said compliant layer comprises depositing a curable liquid over said face of said wafer. 
     
     
         5 . A method as claimed in  claim 2 , wherein said compliant layer is selected from the group consisting of silicone, flexibilized epoxy, fluoropolymer, thermoplastic polymer and polyimide. 
     
     
         6 . A method as claimed in  claim 2 , further comprising, after forming the bond ribbons, forming an encapsulant layer overlying said bond ribbons, wherein said encapsulant layer comprises a plurality of apertures, each aperture aligned with a respective terminal of said terminals. 
     
     
         7 . The method as claimed in  claim 6 , further comprising providing solder masses on the terminals after forming said encapsulant layer. 
     
     
         8 . A method as claimed in  claim 7 , wherein said encapsulant layer is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel. 
     
     
         9 . A method as claimed in  claim 2 , wherein said forming said compliant layer comprises forming said sloping surface to have a first curved transition region adjoining the top surface of said compliant layer and a second curved transition region adjoining the bottom surface of said compliant layer, the first and second transition regions having respective radii of curvature. 
     
     
         10 . A method as claimed in  claim 9 , wherein said compliant layer is readily compressible in directions transverse to its surfaces and said bond ribbon extending along said portion thereof is flexible, such that said compliant layer permits movement of said flexible bond ribbon in directions transverse to the first and second transition regions of the at least one sloping surface. 
     
     
         11 . A method as claimed in  claim 2 , further including, before forming said bond ribbons, depositing a barrier metal atop said contacts. 
     
     
         12 . A method of making a plurality of semiconductor chip packages comprising:
 forming a compliant layer overlying a face of an undiced semiconductor wafer so as to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in said undiced wafer, each semiconductor chip having a plurality of contacts at said face,   wherein each said portion of said compliant layer has a bottom surface adjacent said face, a flat top surface facing away from the bottom surface, and a sloping surface between said top and bottom surfaces;   then, for each of a plurality of said portions, depositing an electrically conductive material onto a contact of a respective semiconductor chip, and onto said sloping surface and said top surface of said portion to form a bond ribbon having a terminal integral with said bond ribbon; and   then separating said packages from one another comprising dicing said wafer at boundaries of said semiconductor chips.   
     
     
         13 . The method as claimed in  claim 12 , wherein said depositing said electrically conductive material is performed to form each of said bond ribbons. 
     
     
         14 . The method as claimed in  claim 12 , wherein said compliant layer is selected from the group consisting of silicone, flexibilized epoxy, fluoropolymer, thermoplastic polymer and polyimide. 
     
     
         15 . The method as claimed in  claim 13 , further comprising forming an encapsulant layer overlying said bond ribbons, wherein said encapsulant layer comprises a plurality of apertures, each aperture aligned with a respective terminal of said terminals. 
     
     
         16 . A method as claimed in  claim 15 , wherein said encapsulant layer is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel. 
     
     
         17 . A method of making a plurality of semiconductor chip packages comprising:
 forming a compliant layer overlying a face of an undiced semiconductor wafer so as to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in said undiced wafer, each semiconductor chip having a plurality of contacts at said face,   wherein each said portion of said compliant layer has a bottom surface adjacent said face, a flat top surface facing away from the bottom surface, and a sloping surface between said top and bottom surfaces;   then for each of a plurality of said portions, depositing metal by at least one of sputtering or plating onto a contact of a respective semiconductor chip, and onto said sloping surface and said top surface of said portion to form a plurality of bond ribbons and terminals integral with said bond ribbons on each of said portions of said compliant layer; and   then separating said packages from one another comprising dicing said wafer at boundaries of said semiconductor chips.   
     
     
         18 . The method as claimed in  claim 17 , wherein said depositing comprises sputtering. 
     
     
         19 . The method as claimed in  claim 17 , wherein said depositing comprises plating. 
     
     
         20 . The method as claimed in  claim 18 , wherein said depositing comprises sputtering a first metal layer onto said contacts and said portions of said compliant layer, and then plating a second metal layer onto said first metal layer. 
     
     
         21 . The method as claimed in  claim 17 , wherein said forming said compliant layer comprises depositing a curable liquid over said face of said wafer.