US2015187719A1PendingUtilityA1

Trace Design for Bump-on-Trace (BOT) Assembly

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Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Dec 30, 2013Filed: Dec 30, 2013Published: Jul 2, 2015
Est. expiryDec 30, 2033(~7.4 yrs left)· nominal 20-yr term from priority
Inventors:Yen-Liang LinChen-Shien ChenTin-Hao Kuo
H10W 72/07236H10W 72/072H10W 72/07221H10W 90/724H10W 72/244H10W 72/07254H10W 72/221H10W 72/07252H10W 72/253H10W 72/225H10W 72/252H10W 72/242H10W 72/232H10W 72/287H05K 3/3436H10W 90/701H05K 2203/1173H05K 2201/10674H10W 80/732H10W 72/932H10W 72/931H10W 72/923H10W 72/29H10W 72/012H01L 2224/16012H01L 2224/16113H01L 2224/8112H01L 2224/81815H01L 2224/16227H01L 24/81H01L 24/16Y02P70/50
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Claims

Abstract

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of forming a bump-on-trace (BOT) assembly, comprising:
 forming a landing trace on a substrate;   positioning a conductive pillar over the landing trace such that the conductive pillar extends at least to an end of the landing trace; and   reflowing a solder feature between the landing trace and the conductive pillar to electrically couple the landing trace to the conductive pillar.   
     
     
         2 . The method of  claim 1 , further comprising positioning the conductive pillar over the landing trace such that the conductive pillar overhangs the end of the landing trace. 
     
     
         3 . The method of  claim 1 , further comprising positioning the conductive pillar such that a length of the landing trace within a conductive pillar periphery is about 20% to about 100% of a diameter of the conductive pillar. 
     
     
         4 . The method of  claim 1 , further comprising positioning the conductive pillar such that a length of the landing trace within a conductive pillar periphery is less than a diameter of the conductive pillar. 
     
     
         5 . The method of  claim 1 , further comprising reducing a length of the landing trace relative to a length of a neighboring trace prior to the positioning of the conductive pillar. 
     
     
         6 . The method of  claim 1 , further comprising removing a portion of the landing trace to generate an augmented wetting area prior to the positioning of the conductive pillar. 
     
     
         7 . The method of  claim 1 , wherein the solder feature abuts an end surface and both sidewalls of the landing trace after the reflowing of the solder feature. 
     
     
         8 . A method of forming a bump-on-trace (BOT) assembly, comprising:
 forming a landing trace on a substrate;   generating an augmented wetting area; and   applying solder over the augmented wetting area of the landing trace to electrically couple the landing trace to a conductive pillar.   
     
     
         9 . The method of  claim 8 , wherein the augmented wetting area includes an end surface of the landing trace. 
     
     
         10 . The method of  claim 8 , wherein the augmented wetting area includes an end surface of the landing trace and a portion of both opposing sidewalls of the landing trace. 
     
     
         11 . The method of  claim 8 , wherein the augmented wetting area includes at least one recess in the landing trace. 
     
     
         12 . The method of  claim 8 , wherein the augmented wetting area includes a plurality of recesses in the landing trace. 
     
     
         13 . The method of  claim 8 , further comprising removing a portion of the landing trace to generate the augmented wetting area. 
     
     
         14 . The method of  claim 8 , further comprising removing a portion of the landing trace such that a length of the landing trace within a conductive pillar periphery is about 20% to about 100% of a diameter of the conductive pillar. 
     
     
         15 . The method of  claim 8 , further comprising aligning the conductive pillar such that a periphery of the conductive pillar extends at least to an end of the landing trace. 
     
     
         16 . The method of  claim 8 , further comprising aligning the conductive pillar such that a periphery of the conductive pillar overhangs an end of the landing trace. 
     
     
         17 . A bump-on-trace (BOT) interconnection for a package, comprising:
 a landing trace including a distal end;   a conductive pillar extending at least to the distal end of the landing trace; and   a solder feature electrically coupling the landing trace and the conductive pillar.   
     
     
         18 . The BOT interconnection of  claim 17 , wherein the conductive pillar overhangs the distal end of the landing trace. 
     
     
         19 . The BOT interconnection of  claim 17 , wherein the landing trace has a shorter length than a neighboring trace in the package. 
     
     
         20 . The BOT interconnection of  claim 17 , wherein the solder feature engages an end surface and opposing sidewalls of the landing trace.

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