Three-dimensional system-in-a-package

Abstract

A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having at least a portion having a thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

1 . A method of making a dielectric assembly, comprising:
 forming openings in a dielectric region overlying a first surface of a first element, electrically conductive elements of the first element being exposed within the openings; then   depositing a metal onto the dielectric region and into the openings to form second electrically conductive elements contacting the conductive elements and the dielectric region;   stacking at least one second element at least partly overlying the first surface of the first element with a bonding layer between the first and second elements, the second element having a first surface facing away from the first element and electrically conductive elements exposed thereat;   forming second openings in a second dielectric region overlying a first surface of the second element, electrically conductive elements of the second element being exposed within the second openings;   depositing a metal onto a surface of the second dielectric region and into the second openings to form third electrically conductive elements contacting the conductive elements of the second element and the second dielectric region, at least one of the third conductive elements directly contacting at least one of the second conductive elements at a location above the first surface of the first element; and   stacking at least one third element at least partly overlying the first surface of the second element with a second bonding layer between the second and third elements, the third element fully overlying at least one second and at least one third conductive element,   wherein the first, second and third elements are substantially planar and at least one of the first, second and third elements is a microelectronic element having a plurality of active circuit elements.