Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a surface including a plurality of portions;   a dielectric material over the surface, wherein the dielectric material includes an aspect ratio that is substantially equal to or greater than a predetermined value.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a liner between a portion of the plurality of portions and the dielectric material. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the dielectric material includes an impurity having a concentration distributed in a linear manner throughout the dielectric material. 
     
     
         4 . The semiconductor of  claim 3 , wherein the impurity includes fluorine. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the dielectric material has an impurity with a concentration substantially constant throughout the dielectric material. 
     
     
         6 . The semiconductor of  claim 5 , wherein the impurity includes phosphorous. 
     
     
         7 . The semiconductor of  claim 1 , further comprising a plurality of conductors wherein each of the conductors includes a sidewall that is a portion of the surface. 
     
     
         8 . A semiconductor structure, comprising:
 a plurality of conductors;   a spacer disposed on a sidewall of each of the plurality of conductors;   a liner on the spacer and a surface of each of the plurality of conductors; and   a phosphorous doped dielectric material between two conductors of the plurality of conductors, wherein a phosphorous concentration throughout the phosphorous doped dielectric material is substantially constant.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein the phosphorous doped dielectric material includes a thickness substantially equal to a height of the plurality of conductors. 
     
     
         10 . The semiconductor structure of  claim 8 , wherein the phosphorous doped dielectric material includes an aspect ratio equal to or greater than about 2.4. 
     
     
         11 . The semiconductor structure of  claim 8 , wherein the dielectric material has a width smaller than 30 nm. 
     
     
         12 . The semiconductor structure of  claim 8 , wherein the phosphorous doped dielectric material further comprises fluorine. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein a fluorine concentration is distributed in a linear manner throughout the phosphorous doped dielectric material. 
     
     
         14 . The semiconductor structure of  claim 12 , wherein a fluorine concentration is highest at an interface between the phosphorous doped dielectric material and the liner. 
     
     
         15 . A method of manufacturing a semiconductor structure, comprising:
 forming a surface on substrate;   forming a dielectric layer over the surface;   etching the dielectric layer; and   treating a top surface of the dielectric layer with plasma.   
     
     
         16 . The method of  claim 15 , wherein treating the top surface of the dielectric layer is with phosphorous plasma. 
     
     
         17 . The method of  claim 15 , wherein treating the top surface of the dielectric layer is with oxygen plasma. 
     
     
         18 . The method of  claim 15 , wherein etching the dielectric layer is an NF 3  etch. 
     
     
         19 . The method of  claim 15 , further comprising repeating forming the dielectric layer. 
     
     
         20 . The method of  claim 15  further comprising forming a liner between the surface and the dielectric layer.