Internal plasma grid for semiconductor fabrication
Abstract
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid may have slots of a particular aspect ratio which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The lower sub-chamber plasma has a lower electron density, lower effective electron temperature, and higher negative ion:positive ion ratio as compared to the upper sub-chamber plasma. The disclosed embodiments may result in an etching process having good center to edge uniformity, selectivity, profile angle, and Iso/Dense loading.
Claims
exact text as granted — not AI-modified1 . An apparatus for etching a feature on a substrate, the apparatus comprising:
a chamber defining an interior where a plasma can be provided; a substrate holder for holding a substrate in the chamber during etching; a plasma generator for producing a plasma within the chamber; and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, wherein the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber, wherein the grid comprises a plurality of slots that extend substantially radially outwards that substantially prevent formation of induced current in the grid when the plasma is produced within the chamber.
2 . The apparatus of claim 1 , further comprising a controller designed or configured to produce the plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber,
wherein the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and wherein the electron density in the lower zone plasma is about 5×10 9 cm−3 or less, and is less than the electron density in the upper zone plasma.
3 . The apparatus of claim 2 , wherein the controller is further designed or configured to apply a bias to the grid.
4 . The apparatus of claim 2 , wherein the controller is further designed or configured to apply a bias to the substrate holder.
5 . The apparatus of claim 2 , wherein the controller is further designed or configured to deliver an etchant gas to the chamber.
6 . The apparatus of claim 2 , wherein the controller is further designed or configured to provide a pressure of less than about 2000 mTorr in the chamber while the plasma etches the substrate.
7 . The apparatus of claim 2 , wherein the controller is further designed or configured to produce an ion-ion plasma in the lower sub-chamber.
8 . The apparatus of claim 1 , wherein the grid has an average thickness of between about 1 and 50 mm.
9 . The apparatus of claim 1 , wherein the slots of the grid have a height to width aspect ratio of between about 0.3-5.
10 . The apparatus of claim 1 , wherein the slots are separated from azimuthally adjacent slots by no more than about 60 degrees.
11 . The apparatus of claim 1 , wherein the plasma generator comprises a coil disposed above a ceiling of the chamber.
12 . (canceled)
13 . The apparatus of claim 1 , further comprising a vacuum connection.
14 . (canceled)
15 . A grid for use in connection with a semiconductor etching apparatus, comprising:
a plate having a diameter that is substantially the same as the diameter of a standard semiconductor substrate for semiconductor device fabrication; a plurality of slots that extend substantially radially outwards in the plate to substantially prevent formation of induced current in the plate when the plate is exposed to plasma; wherein the slots have an aspect ratio that is between about 0.3-5.
16 . The grid of claim 15 , wherein the grid, when placed in a processing chamber of a semiconductor etching apparatus, thereby dividing the processing chamber into an upper sub-chamber and a lower sub-chamber, and exposed to a plasma generated in the upper sub-chamber, operates to maintain a lower electron density in the lower sub-chamber that is at least about 10 times lower than an upper electron density in the upper sub-chamber.
17 . The grid of claim 16 , wherein the grid operates to maintain the lower electron density at least about 100 times lower than the upper electron density.
18 . The grid of claim 15 , wherein the standard semiconductor substrate has a diameter of about 300 mm or about 450 mm.
19 . The grid of claim 15 , wherein azimuthally adjacent slots are separated by at least about 10°, and by no more than about 60°.
20 . The grid of claim 15 , wherein the grid comprises metal.
21 . The grid of claim 15 , wherein the grid comprises an insulative material.
22 . A method of etching a feature on a substrate, the method comprising:
providing the substrate to a substrate holder in a chamber comprising a plasma generator and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, wherein the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber; generating a plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber; and etching the feature in the substrate by interaction of the lower zone plasma with the substrate, wherein the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and wherein the electron density in the lower zone plasma is about 5×10 9 cm −3 or less, and is less than the electron density in the upper zone plasma.
23 - 28 . (canceled)Join the waitlist — get patent alerts
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