Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process

Abstract

A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.

What is claimed is: 
     
         1 . A method for manufacturing a trench MOSFET with embedded schottky rectifier, comprising:
 forming a plurality of gate trenches in an epitaxial layer of a first conductivity type by applying a trench mask and a trench etching;   depositing conductive material padded by a gate oxide layer to fill said gate trenches;   forming a plurality of body regions of a second conductivity type in an upper portion of said epitaxial layer;   depositing a contact interlayer over a top surface of said conductive material and said body regions;   forming a plurality of contact openings in said contact interlayer by applying a contact mask and a contact etching to remove contact interlayer from said contact openings;   forming a plurality of source regions of said first conductivity type near the top surface of said body regions self-aligned to said contact mask by performing source ion implantation through said contact openings and performing a source diffusion without requiring a source mask; and   further etching said contact openings through said source regions and said body regions, and extending into said epitaxial layer to form trenched source-body contacts having a depth shallower than said gate trenches.   
     
     
         2 . The method of  claim 1 , wherein said conductive material is etched to leave necessary portion within said gate trenches and have a top surface not higher than said epitaxial layer. 
     
     
         3 . The method of  claim 1 , wherein said conductive material is remained in said gate trenches having a top surface higher than said epitaxial layer when forming terrace gate structure. 
     
     
         4 . The method of  claim 1 , wherein said body regions can be formed without requiring a body mask when forming a termination area comprising multiple trenched floating gates. 
     
     
         5 . The method of  claim 1 , wherein after etching said contact openings into said epitaxial layer, further comprising carrying out a first angle ion implantation with a dopant of said second conductivity type with angle α1 respective to a vertical line through said contact openings to form a first anti-punch through implant region along an upper portion of sidewalls of said trenched source-body contacts below said source regions. 
     
     
         6 . The method of  claim 5 , after forming said first anti-punch through implant region, further comprising carrying out a second angle ion implantation with a dopant of said second conductivity type with angle α2 respective to the vertical line through said contact openings to form a second anti-punch through implant region surrounding bottoms and a lower portion of sidewalls of said trenched source-body contacts below said first anti-punch through implant region, wherein the dopant dose in said second angle ion implantation is less than the dopant dose in said first angle ion implantation, wherein said angle α 2  is less than said angle α 1  respective to the vertical line 
     
     
         7 . The method of  claim 1 , wherein depositing said contact interlayer comprises successively depositing an un-doped oxide layer and a PSG or BPSG layer onto the top surface of said gate trenches and said body regions. 
     
     
         8 . The method of  claim 6 , after carrying out said second angle ion implantation, further comprising etching said PSG or BPSG layer to enlarge top width of said contact openings.