Methods and apparatuses for three dimensional integrated circuits
Abstract
Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An electronic device structure for a three-dimensional integrated circuit comprising,
a substrate having a hole for through hole metallization interconnects; a metallization barrier layer lining the walls of the hole; a conformal metal deposited in the hole by a wet chemical process forming an outer core, and a material deposited by a dry chemical process forming an inner core within the outer core.
2 . The electronic device structure of claim 1 , wherein the metallization barrier layer comprises tantalum nitride.
3 . The electronic device structure of claim 1 , wherein the outer core comprises copper.
4 . The electronic device structure of claim 1 , wherein the outer core comprises copper and the inner core comprises copper.
5 . The electronic device structure of claim 1 , wherein the outer core comprises copper and the inner core comprises silicon, silicon carbide, silicon dioxide, silicon nitride, aluminum oxide, or aluminum nitride.
6 . The electronic device structure of claim 1 , wherein the outer core comprises copper and the inner core comprises tantalum, tantalum carbide, tantalum nitride, ruthenium, or cobalt.Join the waitlist — get patent alerts
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