Through via process

Abstract

A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, wherein the top surfaces of the ILD layer, the via plug and the contact plug are leveled off, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug.

What is claimed is: 
     
         1 . A semiconductor component, comprising:
 a semiconductor substrate including an integrated circuit (IC) component,   an interlayer dielectric (ILD) layer formed on said semiconductor substrate;   a contact plug formed in said ILD layer and electrically connected to said IC component;   a via plug formed in said ILD layer and extending through a portion of said semiconductor substrate, wherein the top surfaces of said ILD layer, said via plug and said contact plug are leveled off; and   an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of said interconnection structure is electrically connected to the exposed portions of said contact plug and said via plug.   
     
     
         2 . The semiconductor component of  claim 1 , wherein said via plug comprises copper or copper-based alloy. 
     
     
         3 . The semiconductor component of  claim 1 , wherein said contact plug is formed of tungsten or tungsten-based alloy. 
     
     
         4 . The semiconductor component of  claim 1 , further comprising a passivation layer lining the bottom and sidewalls of said via plug. 
     
     
         5 . The semiconductor component of  claim 4 , where said passivation layer comprises silicon oxide, silicon nitride, or combinations thereof.