US2011186989A1PendingUtilityA1

Semiconductor Device and Bump Formation Process

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Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Feb 4, 2010Filed: Sep 16, 2010Published: Aug 4, 2011
Est. expiryFeb 4, 2030(~3.5 yrs left)· nominal 20-yr term from priority
Inventors:Yi-Li HsiaoChen-Hua YuShin-Puu JengChih-Hang TungCheng-Chang Wei
H10W 72/019H10W 72/01953H10W 72/01955H10W 72/245H10W 72/234H10W 72/01257H10W 72/01255H10W 72/01215H10W 72/283H10W 72/20H10D 64/011H10W 72/07236H10W 72/287H10W 72/012H10W 72/90H10W 72/00H10W 20/063H10W 90/701
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Claims

Abstract

A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising:
 a semiconductor substrate;   a pad region on the semiconductor substrate;   a solder bump overlying and electrically connected to the pad region; and   a metal cap layer formed on at least a portion of the solder bump;   wherein the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the metal cap layer comprises nickel. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the metal cap layer comprises palladium. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the metal cap layer comprises gold. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the metal cap layer comprises copper. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the solder bump comprises a lead-free solder material. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the metal cap layer is formed on the entire surface of the solder bump. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the metal cap layer is formed on the lower sidewall surface of the solder bump. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the metal cap layer is formed on the middle sidewall surface of the solder bump. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the solder bump comprises a bottom portion laterally spreading outside the metal cap layer. 
     
     
         11 . A packaging assembly, comprising:
 a semiconductor substrate;   a package substrate; and   a bump structure disposed between and electrically connecting the semiconductor substrate and the package substrate;   wherein the bump structure comprises a solder bump and a metal cap layer covering at least a portion of the solder bump, and the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.   
     
     
         12 . The packaging assembly of  claim 11 , wherein the metal cap layer comprises at least one of nickel, palladium and gold. 
     
     
         13 . The packaging assembly of  claim 11 , wherein the metal cap layer comprises copper. 
     
     
         14 . The packaging assembly of  claim 11 , wherein the solder bump comprises a lead-free solder material. 
     
     
         15 . The packaging assembly of  claim 11 , wherein the solder bump comprises a portion laterally spreading outside the metal cap layer. 
     
     
         16 . A method of forming a semiconductor device, comprising:
 forming a solder material layer on a semiconductor substrate;   performing a thermally reflow process on the solder material layer; and   forming a metal cap layer on at least a portion of the solder material layer;   wherein the metal cap layer a melting temperature greater than a melting temperature of the solder material layer.   
     
     
         17 . The method of  claim 16 , wherein the metal cap layer comprises at least one of nickel, palladium and gold. 
     
     
         18 . The method of  claim 16 , wherein the metal cap layer is formed after the thermally reflow process. 
     
     
         19 . The method of  claim 16 , wherein the metal cap layer is formed before the thermally reflow process. 
     
     
         20 . The method of  claim 16 , wherein the solder material layer is a solder pillar, and the metal cap layer is formed to cover at least a portion of the sidewall surface of the solder pillar.

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