Metallic bump structure without under bump metallurgy and a manufacturing method thereof

Abstract

The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, a thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

1 . A method of forming a metallic bump on an I/O pad on an active side of a semiconductor device, comprising the steps of:
 arranging an isolative layer on said active side of said semiconductor device;   forming a via in said isolative layer above said I/O pad;   forming a thin metallic layer on a top surface of said isolative layer and in said via connecting said I/O pad;   forming a first plating resist on a top surface of said thin metallic layer above said isolative layer, said first plating resist having a first opening at least exposing said via coated with said thin metallic layer; and   plating a metallic material in said first opening until an appropriate thickness is reached.   
     
     
         2 . The method according to  claim 1 , further comprising the step of:
 if said I/O pad is made of aluminum or said I/O pad has an anti-oxidation layer made of aluminum, forming a zinc layer on a top surface of said aluminum I/O pad or said aluminum anti-oxidation layer before arranging said isolative layer.   
     
     
         3 . The method according to  claim 1 , further comprising the step of:
 if said I/O pad is made of aluminum or said I/O pad has an anti-oxidation layer made of aluminum, forming a zinc layer on a top surface of said aluminum I/O pad or said aluminum anti-oxidation layer after said via is formed.   
     
     
         4 . The method according to  claim 1 , further comprising the step of:
 if said I/O pad is made of copper and said I/O pad has an anti-oxidation layer, removing said anti-oxidation layer before arranging said isolative layer.   
     
     
         5 . The method according to  claim 1 , further comprising the step of:
 if said I/O pad is made of copper and said I/O pad has an anti-oxidation layer, removing said anti-oxidation layer after said via is formed.   
     
     
         6 . The method according to  claim 1 , wherein said isolative layer is in one of a temporarily cured state and a liquid state, and is stacked on said active side first; said isolative layer is permanently solidified; said via is then formed by removing a part of said isolative layer above said I/O pad; and said thin metallic layer is formed on said top surface of said isolative layer and in said via. 
     
     
         7 . The method according to  claim 1 , wherein said isolative layer is in a liquid state or a temporarily cured state, and is stacked on said active side first; said isolative layer is permanently solidified; said thin metallic layer is then formed on said top surface of said isolative layer; said via is then formed by removing a part of said isolative layer and said thin metallic layer above said I/O pad; and said thin metallic layer is formed again in said via. 
     
     
         8 . The method according to  claim 1 , further comprising the step of:
 thickening said thin metallic layer before forming said first plating resist.   
     
     
         9 . The method according to  claim 1 , wherein said thin metallic layer is made of one of copper and nickel. 
     
     
         10 . The method according to  claim 1 , wherein said metallic material is one of gold, copper, tin, nickel, solder, and a combination thereof. 
     
     
         11 . The method according to  claim 1 , further comprising the steps of:
 removing said first plating resist and part of said thin metallic layer beneath said first plating resist; and   forming a coating layer for anti-oxidation at least on a top surface of said metallic bump.   
     
     
         12 . The method according to  claim 1 , further comprising the steps of:
 forming a coating layer for anti-oxidation on a top surface of said metallic bump; and   removing said first plating resist and part of said thin metallic layer beneath said first plating resist.   
     
     
         13 . The method according to  claim 1 , wherein said first opening further exposes one of a rerouted location and an intermediate location of said metallic bump and a routing trace connecting said rerouted location or intermediate location to said via; and the plating of said metallic material forms said routing trace. 
     
     
         14 . The method according to  claim 13 , further comprising the step of:
 forming a blind hole in said isolative layer at said rerouted location before forming said first plating resist;   wherein said thin metallic layer also covers said blind hole.   
     
     
         15 . The method according to  claim 13 , further comprising the steps of:
 forming a blind hole in said isolative layer at said rerouted location before forming said first plating resist; and   filling said blind hole with a conductive paste before forming said first plating resist.   
     
     
         16 . The method according to  claim 13 , further comprising the steps of:
 forming a second plating resist on a top surface of said first plating resist and said routing trace, said second plating resist having a second opening exposing said rerouted location;   plating a second metallic material in said second opening until an appropriate thickness is achieved; and   forming said metallic bump by removing said first and second plating resists, and a part of said thin metallic layer beneath said first plating resist.   
     
     
         17 . The method according to  claim 16 , wherein said second metallic material is one of gold, copper, tin, nickel, solder, and a combination thereof. 
     
     
         18 . The method according to  claim 16 , further comprising the step of:
 applying a solder mask to cover said routing trace and said via after removing said first and second plating resists.   
     
     
         19 . The method according to  claim 1 , wherein said first opening further exposes a rerouted location of said metallic bump, a routing trace connecting said rerouted location and said via, at least a plating bar connecting a plating electrode of said semiconductor device to a plating net comprising said via, said routing trace, and said metallic bump; and the plating of said metallic material forms said routing trace and said plating bar. 
     
     
         20 . The method according to  claim 19 , further comprising the steps of:
 removing said first plating resists, and part of said thin metallic layer beneath said first plating resist;   applying a solder mask to expose said rerouted location, a part of said plating bar, and said plating electrode;   forming a second plating resist on said solder mask, said second plating resist having a second opening exposing said rerouted location and said plating electrode;   forming said metallic bump by plating a second metallic material in said second opening until an appropriate thickness is achieved; and   removing said second plating resist and said plating bar.   
     
     
         21 . The method according to  claim 20 , wherein said second metallic material is one of gold, copper, tin, nickel, solder, and a combination thereof. 
     
     
         22 . The method according to  claim 19 , further comprising the steps of:
 arranging a second isolative layer and a second thin metallic layer in this order on said active side of said semiconductor device, said second isolative layer and said second thin metallic layer having a second via at said intermediate location;   forming a second thin metallic layer at least in said second via;   forming a second plating resist on a top surface of said second thin metallic layer, said second plating resist having a second opening exposing said second via coated with said second thin metallic layer, said rerouted location of said metallic bump, and a second routing trace connecting said rerouted location to said second via;   forming said second routing trace by plating a metallic material in said second opening until an appropriate thickness is achieved;   forming a third plating resist on a top surface of said second plating resist and said second routing trace, said third plating resist having a third opening exposing said rerouted location;   plating a third metallic material in said third opening until an appropriate thickness is achieved; and   forming said metallic bump by removing said second and third plating resists, and part of said second thin metallic layer beneath said second plating resist.   
     
     
         23 . The method according to  claim 22 , further comprising the step of:
 forming a blind hole in said second isolative layer and said second thin metallic layer at said rerouted location before forming said second thin metallic layer;   wherein said second thin metallic layer further covers said blind hole.   
     
     
         24 . The method according to  claim 22 , further comprising the steps of:
 forming a blind hole in said second isolative layer and said second thin metallic layer at said rerouted location before forming said second thin metallic layer; and   filling said blind hole with a conductive paste before forming said second plating resist.   
     
     
         25 . The method according to  claim 21 , wherein said third metallic material is one of gold, copper, tin, nickel, solder, and a combination thereof. 
     
     
         26 . The method according to  claim 1 , wherein said semiconductor device is one of a semiconductor wafer and a part of a semiconductor wafer after separation.