Runtime configurable arithmetic and logic cell

Abstract

A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.

1 - 3 . (canceled) 
     
     
         4 . An integrated circuit comprising:
 a plurality of processing cells interconnected by a network;   wherein:
 at least some of the cells have a configurable arithmetic logic unit (ALU); and 
 at least some of the cells are configurable, perform at least one of arithmetic and logic data processing, and have at least one register, a clock supply of the at least one register being suppressible. 
   
     
     
         5 . The integrated circuit according to  claim 4 , wherein the suppressibility of the clock supply depends on acceptability, by a receiver, of output data of the at least some of the cells that perform the at least one of the arithmetic and logic processing. 
     
     
         6 . The integrated circuit according to  claim 4 , wherein at least some of the processing cells are runtime configurable. 
     
     
         7 . The integrated circuit according to  claim 4 , wherein the at least some of the cells having the configurable ALU have at least one input register. 
     
     
         8 . The integrated circuit according to  claim 4 , wherein the at least some of the cells having a configurable ALU have at least one output register. 
     
     
         9 . The integrated circuit according to  claim 4 , wherein the clock supply is suppressible for power saving. 
     
     
         10 . The integrated circuit according to  claim 4 , wherein the suppressibility of the clock supply depends on availability of input data to the at least some of the cells that perform the at least one of the arithmetic and logic processing. 
     
     
         11 . The integrated circuit according to  claim 10 , wherein each of the at least some of the cells having the configurable ALU has at least 3 inputs. 
     
     
         12 . The integrated circuit according to  claim 11 , wherein the network is configurable. 
     
     
         13 . The integrated circuit according to  claim 12 , wherein the integrated circuit is a Field Programmable Gate Array (FPGA) integrated circuit. 
     
     
         14 . An integrated circuit comprising:
 a plurality of processing cells interconnected by a network;   wherein:
 at least some of the cells have a configurable arithmetic logic unit (ALU); and 
 at least some of the cells are configurable, perform at least one of arithmetic and logic data processing, and have at least one register, a clock supply to the at least one register being configurably suppressible. 
   
     
     
         15 . The integrated circuit according to  claim 14 , wherein at least some of the processing cells are runtime configurable. 
     
     
         16 . The integrated circuit according to  claim 14 , wherein each of the at least some of the cells having the configurable ALU has at least 3 inputs. 
     
     
         17 . The integrated circuit according to  claim 16 , wherein the at least some of the cells having the configurable ALU have at least one input register. 
     
     
         18 . The integrated circuit according to  claim 16 , wherein the at least some of the cells having the configurable ALU have at least one output register. 
     
     
         19 . The integrated circuit according to  claim 18 , wherein the integrated circuit is a Field Programmable Gate Array integrated circuit (FPGA). 
     
     
         20 . The integrated circuit according to  claim 14 , wherein the network is configurable. 
     
     
         21 . The integrated circuit according to  claim 14 , wherein the clock supply is suppressible for power saving. 
     
     
         22 . An integrated circuit comprising:
 a plurality of processing cells interconnected by a network;   wherein:
 at least some of the cells have a configurable arithmetic logic unit (ALU); and 
 at least some of the cells are configurable, perform at least one of arithmetic and logic data processing, and have at least one register, an arrangement being provided with the at least one register for disabling a clock supply of the at least one register. 
   
     
     
         23 . The integrated circuit according to  claim 22 , wherein the disablement of the clock supply depends on availability of input data to the at least some of the cells that perform the at least one of the arithmetic and logic processing. 
     
     
         24 . The integrated circuit according to  claim 22 , wherein the disablement of the clock supply depends on acceptability, by a receiver, of output data of the at least some of the cells that perform the at least one of the arithmetic and logic processing. 
     
     
         25 . The integrated circuit according to  claim 22 , wherein each of the at least some of the cells having a configurable ALU has at least 3 inputs. 
     
     
         26 . The integrated circuit according to  claim 25 , wherein each of the at least some of the cells having a configurable ALU has at least one input register. 
     
     
         27 . The integrated circuit according to  claim 26 , wherein at least some of the processing cells are runtime configurable. 
     
     
         28 . The integrated circuit according to  claim 22 , wherein each of the at least some of the cells having a configurable ALU has at least one output register. 
     
     
         29 . The integrated circuit according to  claim 22 , wherein the network is configurable. 
     
     
         30 . The integrated circuit according to  claim 22 , wherein the disablement of the clock supply provides power saving. 
     
     
         31 . The integrated circuit according to  claim 22 , wherein the integrated circuit is a Field Programmable Gate Array (FPGA) integrated circuit.