Assignee
VORBACH MARTIN
DE·49 granted patents·23 pending applications·669 citations·filing 2000–2015
Top patents by PatentIndex Score
72 records- 0197US9043769B2Optimization of loops and data flow sections in multi-core processor environmentVORBACH MARTIN·Filed 2010·Granted May 26, 2015·46 cites·7 claims
- 0297US7928763B2Multi-core processing systemVORBACH MARTIN·Filed 2010·Granted Apr 19, 2011·27 cites·60 claims
- 0396US9086973B2System and method for a cache in a multi-core processorVORBACH MARTIN·Filed 2010·Granted Jul 21, 2015·27 cites·38 claims
- 0495US8812820B2Data processing device and methodVORBACH MARTIN·Filed 2009·Granted Aug 19, 2014·50 cites·13 claims
- 0595US8156284B2Data processing method and deviceVORBACH MARTIN·Filed 2003·Granted Apr 10, 2012·129 cites·37 claims
- 0693US9152427B2Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register fileVORBACH MARTIN·Filed 2009·Granted Oct 6, 2015·25 cites·22 claims
- 0792US8869121B2Method for the translation of programs for reconfigurable architecturesVORBACH MARTIN·Filed 2011·Granted Oct 21, 2014·17 cites·13 claims
- 0892US8250503B2Hardware definition method including determining whether to implement a function as hardware or softwareVORBACH MARTIN·Filed 2007·Granted Aug 21, 2012·22 cites·55 claims
- 0991US8914590B2Data processing method and deviceVORBACH MARTIN·Filed 2009·Granted Dec 16, 2014·26 cites·7 claims
- 1091US8686549B2Reconfigurable elementsVORBACH MARTIN·Filed 2009·Granted Apr 1, 2014·23 cites·52 claims
- 1190US11061682B2Advanced processor architectureVORBACH MARTIN·Filed 2015·Granted Jul 13, 2021·6 cites·20 claims
- 1290US9348587B2Providing code sections for matrix of arithmetic logic units in a processorVORBACH MARTIN·Filed 2011·Granted May 24, 2016·9 cites·10 claims
- 1390US9037807B2Processor arrangement on a chip including data processing, memory, and interface elementsVORBACH MARTIN·Filed 2010·Granted May 19, 2015·12 cites·75 claims
- 1490US8099618B2Methods and devices for treating and processing dataVORBACH MARTIN·Filed 2008·Granted Jan 17, 2012·16 cites·8 claims
- 1589US8058899B2Logic cell array and bus systemVORBACH MARTIN·Filed 2009·Granted Nov 15, 2011·17 cites·82 claims
- 1688US8819505B2Data processor having disabled coresVORBACH MARTIN·Filed 2009·Granted Aug 26, 2014·12 cites·52 claims
- 1787US8281265B2Method and device for processing dataVORBACH MARTIN·Filed 2009·Granted Oct 2, 2012·14 cites·21 claims
- 1887US8069373B2Method for debugging reconfigurable architecturesVORBACH MARTIN·Filed 2009·Granted Nov 29, 2011·10 cites·22 claims
- 1986US7822881B2Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)VORBACH MARTIN·Filed 2005·Granted Oct 26, 2010·13 cites·4 claims
- 2085US8407525B2Method for debugging reconfigurable architecturesVORBACH MARTIN·Filed 2011·Granted Mar 26, 2013·5 cites·7 claims
- 2184US8726250B2Configurable logic integrated circuit having a multidimensional structure of configurable elementsVORBACH MARTIN·Filed 2010·Granted May 13, 2014·5 cites·23 claims
- 2284US7996827B2Method for the translation of programs for reconfigurable architecturesVORBACH MARTIN·Filed 2002·Granted Aug 9, 2011·46 cites·80 claims
- 2383US8301872B2Pipeline configuration protocol and configuration unit communicationVORBACH MARTIN·Filed 2005·Granted Oct 30, 2012·11 cites·17 claims
- 2480US8686475B2Reconfigurable elementsVORBACH MARTIN·Filed 2011·Granted Apr 1, 2014·5 cites·58 claims
- 2579US8471593B2Logic cell array and bus systemVORBACH MARTIN·Filed 2011·Granted Jun 25, 2013·4 cites·30 claims
- 2678US8230411B1Method for interleaving a program over a plurality of cellsVORBACH MARTIN·Filed 2000·Granted Jul 24, 2012·16 cites·23 claims
- 2778US7782087B2Reconfigurable sequencer structureVORBACH MARTIN·Filed 2009·Granted Aug 24, 2010·4 cites·7 claims
- 2877US7844796B2Data processing device and methodVORBACH MARTIN·Filed 2004·Granted Nov 30, 2010·23 cites·3 claims
- 2977US7822968B2Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputsVORBACH MARTIN·Filed 2009·Granted Oct 26, 2010·4 cites·138 claims
- 3076US9703538B2Tool-level and hardware-level code optimization and respective hardware modificationVORBACH MARTIN·Filed 2012·Granted Jul 11, 2017·3 cites·8 claims
- 3174US8312301B2Methods and devices for treating and processing dataVORBACH MARTIN·Filed 2009·Granted Nov 13, 2012·4 cites·44 claims
- 3273US8209653B2RouterVORBACH MARTIN·Filed 2008·Granted Jun 26, 2012·5 cites·19 claims
- 3372US8429385B2Device including a field having function cells and information providing cells controlled by the function cellsVORBACH MARTIN·Filed 2002·Granted Apr 23, 2013·10 cites·2 claims
- 3472US8145881B2Data processing device and methodVORBACH MARTIN·Filed 2008·Granted Mar 27, 2012·5 cites·1 claims
- 3569US7840842B2Method for debugging reconfigurable architecturesVORBACH MARTIN·Filed 2007·Granted Nov 23, 2010·2 cites·13 claims
- 3666US8281108B2Reconfigurable general purpose processor having time restricted configurationsVORBACH MARTIN·Filed 2003·Granted Oct 2, 2012·11 cites·5 claims
- 3765US8468329B2Pipeline configuration protocol and configuration unit communicationVORBACH MARTIN·Filed 2012·Granted Jun 18, 2013·1 cites·28 claims
- 3864US10031888B2Parallel memory systemsVORBACH MARTIN·Filed 2012·Granted Jul 24, 2018·1 cites·19 claims
- 3957US2013339797A1Method for debugging reconfigurable architecturesVORBACH MARTIN·Filed 2013·Application pending·0 cites
- 4056US8310274B2Reconfigurable sequencer structureVORBACH MARTIN·Filed 2011·Granted Nov 13, 2012·0 cites·20 claims
- 4156US2009153188A1PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)VORBACH MARTIN·Filed 2009·Application pending·0 cites
- 4255USRE44383EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2008·Granted Jul 16, 2013·0 cites·1 claims
- 4355US2010122064A1Method for increasing configuration runtime of time-sliced configurationsVORBACH MARTIN·Filed 2009·Application pending·0 cites
- 4454US2010095094A1Method for processing dataVORBACH MARTIN·Filed 2009·Application pending·0 cites
- 4554US2009144485A1Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)VORBACH MARTIN·Filed 2009·Application pending·0 cites
- 4653USRE45223EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Oct 28, 2014·0 cites·122 claims
- 4753USRE45109EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Sep 2, 2014·0 cites·14 claims
- 4853USRE44365EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Jul 9, 2013·0 cites·81 claims
- 4953US8312200B2Processor chip including a plurality of cache elements connected to a plurality of processor coresVORBACH MARTIN·Filed 2010·Granted Nov 13, 2012·0 cites·42 claims
- 5053US8156312B2Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control unitsVORBACH MARTIN·Filed 2007·Granted Apr 10, 2012·0 cites·62 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when VORBACH MARTIN files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →