Sidewall-Free CESL for Enlarging ILD Gap-Fill Window

Abstract

An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.

1 . An integrated circuit structure comprising:
 a first gate strip;   a gate spacer on a sidewall of the first gate strip; and   a contact etch stop layer (CESL) comprising a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.   
     
     
         2 . The integrated circuit structure of  claim 1  further comprising a second gate strip adjacent the first gate strip with a gap between the first gate strip and the second gate strip, wherein the bottom portion of the CESL is in the gap. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the bottom portion of the CESL adjoins a bottom portion of the gate spacer. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the bottom portion of the CESL is spaced apart from the gate spacer. 
     
     
         5 . The integrated circuit structure of  claim 1  further comprising a source/drain region adjacent the first gate strip, wherein the bottom portion of the CESL is directly over the source/drain region. 
     
     
         6 . The integrated circuit structure of  claim 5  further comprising a source/drain silicide over and contacting the source/drain region, wherein the bottom portion of the CESL is directly over and contacting the source/drain silicide. 
     
     
         7 . The integrated circuit structure of  claim 6  further comprising:
 an inter-layer dielectric (ILD) over and contacting the CESL; and   a contact plug in the ILD, wherein the contact plug extends into the bottom portion of the CESL and contacts the source/drain silicide.   
     
     
         8 . The integrated circuit structure of  claim 1 , wherein the CESL further comprises a top portion directly over the first gate strip and disconnected from the bottom portion of the CESL. 
     
     
         9 . The integrated circuit structure of  claim 8 , wherein the top portion of the CESL and the bottom portion of the CESL are formed of a same material, and wherein the bottom portion of the CESL is thinner than the top portion of the CESL. 
     
     
         10 . An integrated circuit structure comprising:
 a first conductive strip;   a first spacer on a sidewall of the first conductive strip;   a second conductive strip;   a second spacer on a sidewall of the second conductive strip;   a gap between the first spacer and the second spacer; and   a contact etch stop layer (CESL) comprising:
 a top portion directly over the first conductive strip; and 
 a bottom portion in the gap and disconnected from the top portion, wherein a sidewall of the first spacer does not have any portion of the CESL formed thereon. 
   
     
     
         11 . The integrated circuit structure of  claim 10 , wherein the first conductive strip forms a gate of a first MOS device, and the second conductive strip forms a gate of a second MOS device. 
     
     
         12 . The integrated circuit structure of  claim 11  further comprising:
 a source/drain region adjacent and under the gap; and   a source/drain silicide over and contacting the source/drain region, wherein the bottom portion of the CESL contacts the source/drain silicide.   
     
     
         13 . The integrated circuit structure of  claim 10 , wherein the bottom portion of the CESL is spaced apart from the first spacer and the second spacer. 
     
     
         14 . The integrated circuit structure of  claim 10  further comprising an inter-layer dielectric (ILD) in the gap and separating the first spacer from the bottom portion of the CESL. 
     
     
         15 . The integrated circuit structure of  claim 10 , wherein the bottom portion of the CESL is in contact with the first spacer. 
     
     
         16 . The integrated circuit structure of  claim 10  further comprising a shallow trench isolation (STI) region directly under the first conductive strip and the second conductive strip.