Non-volatile resistance switching memories and methods of making same

Abstract

An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

1 . An integrated circuit memory having a memory cell including:
 a semiconductor having a first active area, a second active area, and a channel between said active areas; and   a layer of a variable resistance material (VRM) directly above said channel.   
     
     
         2 . An integrated circuit memory as in  claim 1  wherein said variable resistance material comprises a correlated electron material (CEM). 
     
     
         3 . An integrated circuit memory as in  claim 1  wherein said memory cell further includes a first conductive layer between said VRM and said channel. 
     
     
         4 . An integrated circuit as in  claim 3  wherein said memory cell includes a second conductive layer directly above said VRM layer. 
     
     
         5 . An integrated circuit as in  claim 3  wherein said first conductive layer directly contacts said channel. 
     
     
         6 . An integrated circuit as in  claim 3  wherein said first conductive layer comprises a plurality of conductive layers. 
     
     
         7 . An integrated circuit as in  claim 1  wherein said memory cell further includes a layer of an insulating material between said VRM and said channel. 
     
     
         8 . An integrated circuit as in  claim 1  wherein said memory cell comprises a field effect transistor (FET). 
     
     
         9 . An integrated circuit as in  claim 8  wherein said memory cell comprises a JFET structure. 
     
     
         10 . An integrated circuit as in  claim 8  wherein said memory cell comprises a MESFET structure. 
     
     
         11 . An integrated circuit as in  claim 8  wherein said memory cell comprises a MOSFET structure. 
     
     
         12 - 20 . (canceled) 
     
     
         21 . A method of making a non-volatile integrated circuit memory, said method comprising:
 depositing a variable resistance material (VRM) on a semiconductor directly above a channel in said semiconductor; and   completing said memory to include said VRM in an active element in said memory.   
     
     
         22 . A method as in  claim 21  wherein said depositing comprises forming a conductor/VRM/conductor stack. 
     
     
         23 . A method as in  claim 22  wherein said forming comprises forming said stack over a JFET channel. 
     
     
         24 . A method as in  claim 21  wherein said depositing comprises depositing a correlated electron material (CEM).