US2010206737A1PendingUtilityA1

Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)

Individually held — no corporate assignee on recordPriority: Feb 17, 2009Filed: Feb 17, 2009Published: Aug 19, 2010
Est. expiryFeb 17, 2029(~2.6 yrs left)· nominal 20-yr term from priority
C25D 5/02C25D 7/123C25D 21/16C25D 3/38H10P 14/47H10W 90/726H10W 90/722H10W 72/952H10W 72/923H10W 72/252H10W 72/244H10W 72/90H10W 20/0245H10W 20/0261H10W 72/019H10W 20/023C25D 5/611C25D 5/18C25D 5/617
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Claims

Abstract

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and/or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe +2 /Fe +3 redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

Claims

exact text as granted — not AI-modified
1 . A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), comprising:
 providing a silicon substrate containing at least one via, wherein the via includes an inner surface having an internal width dimension in the range from about 1.5 microns to about 30 microns, a depth from about 5 microns to about 450 microns and a depth:width aspect ratio of at least 3:1;   optionally, forming a dielectric layer on the inner surface of the via;   forming a barrier layer over the inner surface of the via or over the dielectric layer when present, wherein the barrier layer inhibits diffusion of copper into the silicon substrate;   forming over the barrier layer a basic metal layer of sufficient thickness and coverage of the inner surface of the via to obtain sufficient conductance for subsequent electrolytic deposition of copper;   immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system with the basic metal layer connected as a cathode, the system further comprising an insoluble dimensionally stable anode and a source of copper metal, wherein the electrolytic bath comprises an acid, a source of copper ions, a source of ferrous and/or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and   applying an electrical voltage between the insoluble dimensionally stable anode and the basic metal layer, so that a current flows therebetween for a time sufficient to electrodeposit high purity copper to form a TSV, wherein a Fe +2 /Fe +3  redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from the source of copper metal.   
     
     
         2 . The process of  claim 1  wherein the applying is effective to electrodeposit the high purity copper to completely fill the via. 
     
     
         3 . The process of  claim 1  wherein the applying is effective to electrodeposit the high purity copper to form a copper lining in the via of sufficient thickness to be capable of function as a TSV. 
     
     
         4 . The process of  claim 1  wherein the deposited high purity copper is either substantially free of internal stress or includes a level of internal stress that does not result in bending of the silicon substrate upon subsequent processing. 
     
     
         5 . The process of  claim 1  wherein the deposited copper is substantially free of voids and non-copper inclusions. 
     
     
         6 . The process of  claim 1  wherein the basic metal layer is formed over the barrier layer by one or more of an electroless plating process, a physical deposition process, a chemical vapor deposition process, or a plasma-enhanced chemical vapor deposition process. 
     
     
         7 . The process of  claim 1  wherein the basic metal layer has a thickness in the range from about 0.02 microns to about 0.5 microns. 
     
     
         8 . The process of  claim 1  wherein the basic metal layer comprises copper. 
     
     
         9 . The process of  claim 1  wherein the barrier layer comprises tantalum. 
     
     
         10 . The process of  claim 1  wherein the dielectric layer comprises silicon dioxide. 
     
     
         11 . The process of any one of claims  110   claim 1  wherein in the electrolytic bath,
 the acid is sulfuric acid at a concentration in the range from about 50 to about 350 g/l,   the source of copper ions is copper sulfate pentahydrate at a concentration in the range from about  20  to about 250 g/l,   the source of ferrous and/or ferric ions is ferrous sulfate heptahydrate and/or ferric sulfate nonahydrate at a concentration in the range from about 1 to about 120 g/l, and   the at least one additive comprises one or more of a polymeric oxygen-containing compound, an organic sulfur compound, a thiourea compound and a polymeric phenazonium compound.   
     
     
         12 . The process of  claim 1  wherein the electrical voltage is applied in a pulse current or a pulse voltage. 
     
     
         13 . The process of  claim 12  wherein the electrical voltage is applied in a reverse pulse form with bipolar pulses including a forward current pulse and a reverse current pulse. 
     
     
         14 . The process of  claim 13  wherein the duration of the reverse current pulse is adjusted to about 1 to about 20 milliseconds. 
     
     
         15 . The process of  claim 13  wherein the duration of the forward current pulse is adjusted to about 10 to about 200 milliseconds. 
     
     
         16 . The process of  claim 13  wherein peak current density of the forward current pulse at a work piece surface is adjusted to a maximum of about 15 A/dm 2 . 
     
     
         17 . The process of  claim 13  wherein the peak current density of the reverse current pulse at a work piece surface is adjusted to a maximum of about 60 A/dm 2 . 
     
     
         18 . The process of  claim 13  wherein a first current pulse is shifted with respect to a second current pulse by about 180°.

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