Resistive device for high-k metal gate technology and method of making

Abstract

A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

1 . A semiconductor device comprising:
 a semiconductor substrate;   an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material;   an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate; and   a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the second material includes a polysilicon. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the first material includes a silicon oxide. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the active device includes a PMOS device or NMOS device. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the passive device includes a rectangle shape, a dog bone shape, or a polygon shape. 
   
   
       6 . The semiconductor device of  claim 5 , wherein a depth of the shape is associated with the predefined resistivity of the passive device. 
   
   
       7 . The semiconductor device of  claim 1  wherein the isolation structure includes a shallow trench isolation (STI) structure. 
   
   
       8 . A semiconductor device comprising:
 a semiconductor substrate;   an isolation structure formed in the substrate for isolating a first region and second region of the substrate;   a first transistor formed in the first region and a second transistor formed in the second region, the first and second transistors each having a high-k dielectric and metal gate; and   a polysilicon resistor device formed in the isolation structure, wherein a surface of the polysilicon resistor device and a surface of the isolation structure lie on a same plane.   
   
   
       9 . The semiconductor device of  claim 8 , wherein the first and second transistors are each a PMOS device or an NMOS device. 
   
   
       10 . The semiconductor device of  claim 8 , wherein the high-k dielectric includes hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof. 
   
   
       11 . The semiconductor device of  claim 8 , wherein the metal gate includes TiN, TaN, TaC, CoSi, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, TiAl, TiNAl, Al, or combinations thereof 
   
   
       12 . The semiconductor device of  claim 8 , wherein the polysilicon resistor device includes a doped polysilicon material. 
   
   
       13 . A semiconductor device comprising:
 a semiconductor substrate;   a first isolation structure in the substrate for isolating an active region of the substrate;   a transistor formed in the active region, the transistor having a gate structure that includes a high-k dielectric layer and a metal layer; and   a fuse structure formed on the isolation structure, the fuse structure having a link portion that includes the high-k dielectric layer and the metal layer, wherein the link portion does not include a polysilicon layer disposed on the metal layer.   
   
   
       14 . The semiconductor device of  claim 13 , wherein the transistor include a PMOS device or an NMOS device. 
   
   
       15 . The semiconductor device of  claim 13 , wherein the isolation structure includes a shallow trench isolation (STI) structure. 
   
   
       16 . The semiconductor device of  claim 13 , wherein the metal gate includes TiN, TaN, TaC, WN, TiAl, TiNAl, Al, or combinations thereof. 
   
   
       17 . The semiconductor device of  claim 13 , wherein the gate structure of the transistor does not include the polysilicon layer disposed on the metal layer. 
   
   
       18 . The semiconductor device of  claim 13 , wherein the fuse structure includes an eFuse device. 
   
   
       19 . The semiconductor device of  claim 13 , wherein the metal layer of the transistor is co-planar with the metal layer of the fuse structure. 
   
   
       20 . The semiconductor device of  claim 13 , further including a second isolation structure formed in the substrate; and
 a polysilicon resistor disposed within the second isolation structure such that a top surface of the resistor is co-planar with a top surface of the second isolation structure.