Trench moseft with trench gates underneath contact areas of esd diode for prevention of gate and source shortate

Abstract

A trench DMOS transistor having overvoltage protection and prevention for shortage between gate and source when contact trenches are applied includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trench gates extend through the body region and the substrate. An insulating oxide layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer defining the Zener diode region. A plurality of cathode regions of the first conductivity type is formed in undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions. Trench gates underneath the Zener diode act as the buffer layer for prevention of shortage between gate and source.

1 . A trench DMOS transistor having overvoltage protection with prevention of shortage between gate and source from ESD, comprising:
 a substrate of a first conductivity type;   a body region on the substrate, said body region having a second conductivity type;   a source region of the first conductivity type in said body region adjacent to each trench in DMOS area;   a conductive electrode in the trench overlying the insulating layer;   a gate oxide layer that lines along the trench and an insulating layer overlies said body region;   a ESD protection diode on top of said insulating layer; and   trench gates underneath contact areas of said ESD diode;   
     
     
         2 . The transistor of  claim 1 , wherein the ESD protection diode is consisted of multiple in-series back to back Zener poly diodes. 
     
     
         3 . The transistor of  claim 1 , wherein said insulating layer has a thickness ranging from 150 angstroms to 1500 angstroms. 
     
     
         4 . The transistor of  claim 1 , wherein said conductive electrode is doped polysilicon. 
     
     
         5 . The transistor of  claim 1 , wherein said trench gates underneath contact areas of the ESD diode act as buffer layer for prevention of shortage between gate and source. 
     
     
         6 . The transistor of  claim 1 , wherein said contact trenches of source and gate is formed with dry oxide and Si etches and filled with metal plug. 
     
     
         7 . The transistor of  claim 1 , wherein further comprising a drain electrode disposed on a bottom surface of the substrate. 
     
     
         8 . The transistor of  claim 7 , wherein further comprising a source electrode contacted to the source and the body regions.