Semiconductor device and a method for manufacturing the same

Abstract

Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric effective constant of the IMD. In embodiments, a semiconductor device may include a substrate having a source/drain area, a gate electrode formed on the semiconductor substrate, a first inter-metal dielectric layer formed on the semiconductor substrate and having a first damascene pattern, a first barrier layer formed on the damascene pattern, a first metal line formed on the first barrier layer, and a first metal capping layer formed in the first damascene pattern.

1 - 17 . (canceled) 
   
   
       18 . A semiconductor device comprising:
 a semiconductor substrate having a source/drain area;   a gate electrode formed on the semiconductor substrate;   a first inter-metal dielectric layer formed on the semiconductor substrate and having a first damascene pattern;   a first barrier layer formed on the damascene pattern;   a first metal line formed on the first barrier layer; and   a first metal capping layer formed in the first damascene pattern.   
   
   
       19 . The semiconductor device as claimed in  claim 18 , wherein the first metal capping layer is formed on the first metal line in the first damascene pattern. 
   
   
       20 . The semiconductor device as claimed in  claim 18 , wherein the first damascene pattern includes a first via hole and a first trench, and the first metal capping layer is formed in the first trench. 
   
   
       21 . The semiconductor device as claimed in  claim 18 , wherein a predetermined portion of the first barrier layer is positioned at both sides of the first metal capping layer. 
   
   
       22 . The semiconductor device as claimed in  claim 18 , wherein the first metal capping layer includes any one selected from the group consisting of Ti, SiN, SiCN, Tin and Ru. 
   
   
       23 . The semiconductor device as claimed in  claim 18 , wherein a second inter-metal dielectric layer having a second damascene pattern is formed on the first inter-metal dielectric layer, a second barrier layer and the second metal line are formed in the second damascene pattern, and the second barrier layer is formed on the first metal capping layer. 
   
   
       24 . The semiconductor device as claimed in  claim 23 , further comprising a second metal capping layer formed in the second damascene pattern, wherein the second metal capping layer is formed on the second metal line. 
   
   
       25 . The semiconductor device as clamed in  claim 24 , wherein the second damascene pattern includes a second via hole and a second trench, and the second metal capping layer is formed in the second trench.