Multiple-port sram device

Abstract

A multiple-port SRAM cell includes a latch having a first node and a second node for retaining a value and its complement, respectively. The cell has a write port separate from a read port for parallel operation. A number of transistors are used to connect the first and second nodes to a number of bit lines, such as a read port bit line, a read port complementary bit line, a read/write port bit line, and a read/write port complementary bit line. In a layout view of the multiple-port SRAM cell, the read port bit line, read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.

1 . A static random access memory (SRAM) cell having a dedicated read port separated from a write port, the SRAM cell comprising:
 a first and a second bit-line placed in parallel forming a complimentary bit-line pair for the dedicated read port;   a first and second metal line adjacently flanking in both side of and in parallel to the first bit-line, the first and second metal line being formed in the same metal layer as the first bit-line and having a first and second predetermined distance to the first bit-line, respectively; and   a third and fourth metal line adjacently flanking in both side of and in parallel to the second bit-line, the third and fourth metal line being formed in the same metal layer as the second bit-line and having a third and fourth predetermined distance to the second bit-line, respectively,   wherein the first predetermined distance is equal to the third distance and the second predetermined distance is equal to the fourth distance for keeping the first and second bit-lines having balanced capacitance loading.   
   
   
       2 . The SRAM cell of  claim 1 , wherein the first and second bit-lines are formed in the same metal layer and have substantially the same width for having balanced resistance and capacitance loading. 
   
   
       3 . The SRAM cell of  claim 1 , wherein both the first and the third metal lines are high voltage power supply lines while both the second and the fourth metal lines are for word line landing pad. 
   
   
       4 . The SRAM cell of  claim 1 , wherein both the first and the fourth metal lines are high voltage power supply lines while both the second and the third metal lines are for word line landing pad. 
   
   
       5 . The SRAM cell of  claim 1 , wherein both the first and the third metal lines are high voltage power supply lines while both the second and the fourth metal lines are complimentary low voltage power supply lines. 
   
   
       6 . The SRAM cell of  claim 1 , wherein both the first and the fourth metal lines are high voltage power supply lines while both the second and the third metal lines are complimentary low voltage power supply lines. 
   
   
       7 . The SRAM cell of  claim 1  further comprising:
 a latch having a first and a second storage node, the first and the second storage node always storing complimentary values;   a first NMOS transistor having a source, a drain and a gate coupled to the complimentary low voltage supply, the first bit-line and the second node, respectively; and   a second NMOS transistor having a source, a drain and a gate coupled to the complimentary low voltage supply, the second bit-line and the first node, respectively.   
   
   
       8 . The SRAM cell of  claim 7  further comprising:
 a third NMOS transistor having a source and a drain coupled between the drain of the first NMOS transistor and the first bit-line, the third NMOS transistor having a gate coupled to a read word-line; and   a fourth NMOS transistor having a source and a drain coupled between the drain of the second NMOS transistor and the second bit-line, the fourth NMOS transistor having a gate also coupled to the read word-line.   
   
   
       9 . The SRAM cell of  claim 1  further comprising:
 a third and a fourth bit-line placed in parallel forming a complimentary bit-line pair for the write port;   a fifth NMOS transistor having a source and drain coupled between the third bit-line and the first storage node, the fifth NMOS transistor having a gate coupled to a write word-line; and   a sixth NMOS transistor having a source and drain coupled between the fourth bit-line and the second storage node, the sixth NMOS transistor having a gate coupled to the write word-line.   
   
   
       10 . A multiple-port static random access memory (SRAM) device having a plurality of cells, each of which comprises:
 a latch having a first node and a second node for retaining a value and a complementary value, respectively;   a first NMOS transistor coupled between the first node and a read/write port bit line, with its gate controlled by a read/write word line;   a second NMOS transistor coupled between the second node and a read/write port complementary bit line, with its gate controlled by the read/write word line;   a third NMOS transistor having a gate coupled to the second node, and a source coupled to a complementary supply voltage;   a fourth NMOS transistor having a source coupled to a drain of the third NMOS transistor, a drain coupled to a first read port bit line, and a gate coupled to a read word line;   a fifth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage;   a sixth NMOS transistor having a source coupled to a drain of the fifth NMOS transistor, a drain coupled to a first read port complementary bit line, and a gate coupled to the read word line;   a seventh NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage;   an eighth NMOS transistor having a source coupled to a drain of the seventh NMOS transistor, a drain coupled to a second read port bit line, and a gate coupled to the read word line;   a ninth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; and   a tenth NMOS transistor having a source coupled to a drain of the ninth NMOS transistor, a drain coupled to a second read port complementary bit line, and a gate coupled to the read word line,   wherein, in a layout view of the cell, the first read port bit line, first read port complementary bit line, second read port bit line, second read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.   
   
   
       11 . The multiple-port SRAM device of  claim 10 , wherein the first read port bit line, the first read port complementary bit line, the second read port bit line, the second complementary read port bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are constructed on the same metallization layer. 
   
   
       12 . The multiple-port SRAM device of  claim 11 , wherein the read word line and the read/write word line are constructed on a metallization layer above the metallization layer on which the first read port bit line, the first read port complementary bit line, the second read port bit line, the second read port complementary bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are constructed. 
   
   
       13 . The multiple-port SRAM device of  claim 12 , wherein the first read port bit line, the first read port complementary bit line, the second read port bit line, the second read port complementary bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are arranged in substantial parallel with one another. 
   
   
       14 . The multiple-port SRAM device of  claim 13 , wherein the second read port bit line and the first read port bit line are separated by the word line landing pad. 
   
   
       15 . The multiple-port SRAM device of  claim 14 , wherein the first read port bit line and the read/write port bit line are separated by the word line landing pad and the complementary supply voltage line. 
   
   
       16 . The multiple-port SRAM device of  claim 15 , wherein the read/write port bit line and the read/write port complementary bit line are separated by the supply voltage line. 
   
   
       17 . The multiple-port SRAM device of  claim 16 , wherein the write port complementary bit line and the first read port complementary bit line are separated by the complementary supply voltage line and the word line landing pad. 
   
   
       18 . The multiple-port SRAM device of  claim 17 , wherein the first read port complementary bit line and the second read port complementary bit line are separated by the word line landing pad. 
   
   
       19 . The multiple-port SRAM device of  claim 18  has at least six word line landing pads for connecting the read word line and the read/write word line to the gates of the first, second, fourth, sixth, eighth and tenth NMOS transistors. 
   
   
       20 . The multiple-port SRAM device of  claim 10 , wherein a length ratio between the bit line and the word line is less than about ⅕.