Low Latency Massive Parallel Data Processing Device

Abstract

Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.

1 . Data processing device comprising a multidimensional array of ALUs,
 having a least two dimensions where the number of ALUs in the dimension is greater or equal to 2,   adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.   
     
     
         2 . A data processing device in particular according to  claim 1 , wherein
 at least one ALU-chain is provided without registers between ALU-stages of the chain.   
     
     
         3 . A data processing device according to  claim 1 , comprising at least two ALU-pipelines, wherein
 signals are provided between ALUs in different pipelines referring to states and/or conditions in the other pipeline.   
     
     
         4 . A data processing device according to  claim 3 , wherein
 at least one ALU, preferably an ALU in a pipeline,
 preferably each ALU in a pipeline and 
 preferably each ALU in each pipeline, 
   is provided that is capable of
 evaluating a condition and carrying out an operation in response thereto and/or to not carrying out an operation in response thereto, 
   the evaluation and execution or non-execution of operations in response thereto taking place preferably in one clock cycle.   
     
     
         5 . A data processing device according to  claim 4  wherein
 at least one unit, preferably an ALU, is provided capable to execute or non-execute operations in response to an evaluation of another unit,
 preferably one in the same or in a neighboring pipeline, 
 preferably either in the same or in an upstream stage. 
   
     
     
         6 . A data processing device for generating a psuedo-noise pattern comprising
 a plurality of cells forming part or being capable of being used as a reconfigurable array of cells,   and at least one extension comprising
 registers and a number of bit-logic-lines, in particular a stripe of LUTs, each preferably having the same content and/or preferably being a 3:2 LUT.