Semiconductor Constructions and Transistor Gates
Abstract
One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.
Claims
exact text as granted — not AI-modified1 - 40 . (canceled)
41 ) A semiconductor construction comprising:
a semiconductive substrate having a metal mass thereover, the metal mass comprising opposing sidewalls; and an oxide-comprising material above the substrate, wherein at least one sidewall of the metal mass is substantially free of metal oxide.
42 ) The semiconductor construction of claim 41 wherein the metal mass comprises tungsten.
43 ) The semiconductor construction of claim 41 wherein the oxide-comprising material comprises silicon oxide.
44 ) The semiconductor construction of claim 41 wherein the oxide-comprising material is between the metal mass and the substrate.
45 ) The semiconductor construction of claim 41 further comprising semiconductive material between the metal mass and the substrate, the semiconductive material having opposing sidewalls and forming a gate transistor with the metal mass.
46 ) The semiconductor construction of claim 45 wherein at least one of the sidewalls of the semiconductive material is oxidized.
47 ) The semiconductor construction of claim 45 wherein the semiconductive material comprises a dopant.
48 ) The semiconductor construction of claim 47 further comprising a silicide-comprising material along the at least one sidewall of the metal mass.
49 ) The semiconductor construction of claim 48 further comprising a barrier material between the metal mass and the semiconductive material, wherein the barrier material comprises opposing sidewalls, the sidewalls of the barrier material being substantially free of both the silicide-comprising and the metal oxide.
50 ) A transistor gate comprising a semiconductive layer having a metal layer thereover, the semiconductive and metal layers defining a stack having opposing sidewalls, wherein:
an oxide-comprising material is formed along at least one of the sidewalls of the semiconductive layer; and at least one of the sidewalls of the metal layer is substantially free of metal oxide.
51 ) The transistor gate of claim 50 wherein the metal layer comprises tungsten.
52 ) The transistor gate of claim 50 wherein the semiconductive material comprises doped polysilicon.
53 ) The transistor gate of claim 50 wherein the semiconductive material comprise germanium.
54 ) The transistor gate of claim 50 further comprising an insulative cap over the metal layer.
55 ) The transistor gate of claim 54 wherein the insulative cap comprises opposing sidewalls, the oxide-comprising material being formed along at least one of the sidewalls of the insulative cap.
56 ) The transistor gate of claim 50 further comprising insulative material formed along the sidewalls of the stack.
57 ) The transistor gate of claim 50 further comprising a barrier layer between the semiconductive material and the metal layer.
58 ) The transistor gate of claim 57 wherein the barrier layer comprises metal nitride.
59 ) The transistor gate of claim 50 further comprising a silicide-comprising material along the at least one sidewall of the metal layer.
60 ) The transistor gate of claim 50 further comprising source/drain regions associated with the gate.Join the waitlist — get patent alerts
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