Semiconductor device with bonding pad
Abstract
A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern.
Claims
exact text as granted — not AI-modified1 . A semiconductor device with a bonding pad, comprising:
a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface; semiconductor elements disposed on the upper surface of the first substrate in the device area; a first inter-metal dielectric layer on the upper surface of the substrate in the bonding area; a lowermost metal pattern disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad; an opening through the first substrate exposing the lowermost metal pattern; and a bonding wire attached to the lowermost metal pattern through the opening.
2 . The semiconductor device with a bonding pad as claimed in claim 1 , further comprising a scribe line area adjacent to the bonding area.
3 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the semiconductor elements comprise CMOS image sensors.
4 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the first inter-metal dielectric layer comprises a dielectric material having a dielectric constant less than 3.0.
5 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the lowermost metal pattern comprises copper, aluminum, or an alloy thereof.
6 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the lowermost metal pattern is electrically connected to the semiconductor elements.
7 . (canceled)
8 . The semiconductor device with a bonding pad as claimed in claim 1 , further comprising:
a second inter-metal dielectric layer on the lowermost metal pattern; an intermediate metal pattern disposed in the second inter-metal dielectric layer; a third inter-metal dielectric layer on the intermediate metal pattern; an uppermost metal pattern disposed in the third inter-metal dielectric layer; and a second substrate attached to the first substrate so that the semiconductor elements, the lowermost metal pattern and the uppermost metal pattern are interposed therebetween.
9 . The semiconductor device with a bonding pad as claimed in claim 8 , wherein the first substrate and the second substrate comprise silicon.
10 . The semiconductor device with a bonding pad as claimed in claim 8 , wherein the lowermost metal pattern is electrically connected to the intermediate metal pattern by a plurality of first via plugs.
11 . The semiconductor device with a bonding pad as claimed in claim 8 , wherein the intermediate metal pattern is electrically connected to the uppermost metal pattern.
12 . The semiconductor device with a bonding pad as claimed in claim 1 , further comprising an etching stop layer between the lowermost metal pattern and the upper surface of the first substrate.
13 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the lowermost metal pattern comprises a titanium-free copper-aluminum alloy layer.
14 - 23 . (canceled)
24 . The semiconductor device with a bonding pad as claimed in claim 1 , wherein the bonding wire is separated from a sidewall of the opening by a distance.Join the waitlist — get patent alerts
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