Mos transistor for reducing short-channel effects and its production

Abstract

The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas.

1 . A metal-oxide semiconductor (MOS) transistor for reducing short-channel effects, fabricated on a silicon substrate after an isolation module is finished, the MOS transistor comprising a gate stack and source and drain areas,
 wherein the silicon substrate has a groove and the gate stack is formed in the groove.   
   
   
       2 . The MOS transistor for reducing short-channel effects according to  claim 1 , wherein the bottom of the groove is lower than the top surface of the source and drain areas. 
   
   
       3 . The MOS transistor for reducing short-channel effects according to  claim 1 , wherein the area of the groove is not less than that of the gate stack. 
   
   
       4 . The MOS transistor for reducing short-channel effects according to  claim 1 , further comprising a LDD (lightly doped drain) structure. 
   
   
       5 . The MOS transistor for reducing short-channel effects according to  claim 1 , further comprising a halo implantation structure. 
   
   
       6 . The MOS transistor for reducing short-channel effects according to  claim 1 , wherein the gate stack comprises a gate insulation layer and a gate electrode which are layered. 
   
   
       7 . The MOS transistor for reducing short-channel effects according to  claim 1 , further comprising a metal silicide layer which is formed on the source and drain areas. 
   
   
       8 . A manufacturing method of a MOS transistor for reducing short-channel effects, the MOS transistor fabricated on a silicon substrate after an isolation module is finished, the method comprising the following steps:
 (1) forming a groove in the silicon substrate;   (2) carrying out well implantation, anti-punchthrough implantation and threshold-voltage-adjustment implantation;   (3) forming a gate stack in the groove, wherein the gate stack comprises a gate insulation layer and a gate electrode which are layered;   (4) carrying out lightly doped drain implantation and halo implantation;   (5) forming a gate sidewall spacer;   (6) carrying out source and drain implantation to get source and drain areas.   7) forming a metal silicide layer on the source and drain areas.   
   
   
       9 . The fabrication method of a MOS transistor for reducing short-channel effects according to  claim 8 , the step (3) comprising patterning the gate structure in the groove. 
   
   
       10 . The fabrication method of a MOS transistor for reducing short-channel effects according to  claim 8 , the step (1) comprising the following steps:
 (10) patterning the groove corresponding to the gate stack by photolithography;   (11) forming the groove by etching;   (12) optimizing the surface of the silicon substrate.   
   
   
       11 . The fabrication method of a MOS transistor for reducing short-channel effects according to  claim 10 , wherein, in Step (11), the groove is formed by wet etching. 
   
   
       12 . The fabrication method of a MOS transistor for reducing short-channel effects according to  claim 10 , wherein, in Step (12), the surface of the silicon substrate is optimized by oxidation and wet etching.