Trenched mosfets with embedded schottky in the same cell

Abstract

A semiconductor power device includes trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device with a source-body contact trench opened therethrough the source and body regions and extending into an epitaxial layer below the body regions and filled with contact metal plug therein. The semiconductor power device further includes an embedded Schottky diode disposed near a bottom of the source-body contact trench below the contact metal plug wherein the Schottky diode further includes a Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source.

1 . A trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein said semiconductor power device further comprising:
 an insulation layer covering said trenched semiconductor power device with a source-body contact trench opened therethrough and further extending through said body region into an epitaxial region underneath and filled with contact metal plug therein; and   an embedded Schottky diode disposed near a bottom of said source-body contact trench below said contact metal plug wherein said Schottky diode further comprising a Schottky barrier layer directly contacting an epitaxial layer below a bottom of said contact trench thus forming a vertical Schottky diode along a source-drain direction having a barrier height for reducing a leakage current through said embedded Schottky diode during a reverse bias between said drain and said source.   
   
   
       2 . The trenched semiconductor power device of  claim 1  further comprising:
 a contact enhancement dopant region disposed along sidewalls of said source-body contact trench for improving an electrical contact of said contact metal plug and to said body regions.   
   
   
       3 . The trenched semiconductor power device of  claim 1  wherein:
 said embedded Schottky diode further comprising a CoSi2/TiN barrier layer disposed below said contact metal plug directly contacting said epitaxial layer below said contact trench.   
   
   
       4 . The trenched semiconductor power device of  claim 1  wherein: said metal contact plug further comprising a tungsten plug filling in said source-body contact trench for contacting said source and body regions and said vertical Schottky diode disposed below said tungsten plug. 
   
   
       5 . The trenched semiconductor power device of  claim 2  wherein:
 said a contact enhancement dopant region disposed along sidewalls of said source-body contact trench further comprising a P-type body-dopant region having a higher dopant concentration than said body region for improving an electrical contact of said contact metal plug to said body regions.   
   
   
       6 . The trenched semiconductor power device of  claim 1  wherein:
 said embedded Schottky diode further comprising a PtSi barrier layer disposed below said contact metal plug directly contacting said epitaxial layer below said contact trench.   
   
   
       7 . The trenched semiconductor power device of  claim 1  wherein:
 said embedded Schottky diode further comprising a barrier layer having a barrier height larger than 0.5V for reducing a leakage current during a reverse bias between said drain and said source and said barrier layer having a forward voltage drop less than a parasitic body diode between said body region and said epitaxial layer surrounding and below said body region.   
   
   
       8 . The trenched semiconductor power device of  claim 1  wherein:
 the contact metal plug further comprising a Ti/TiN barrier layer surrounding a tungsten core as a source-body contact metal.   
   
   
       9 . The trenched semiconductor power device of  claim 1  further comprising:
 a thin resistance-reduction conductive layer disposed on a top surface covering said insulation layer and contacting said contact metal plug whereby said resistance-reduction conductive layer having a greater area than a top surface of said contact metal plug for reducing a source-body resistance.   
   
   
       10 . The trenched semiconductor power device of  claim 1  further comprising:
 a thin resistance-reduction conductive layer comprising a Ti or Ti/TiN layer disposed on a top surface covering said insulation layer and contacting said contact metal plug whereby said resistance-reduction conductive layer having a greater area than a top surface of said contact metal plug for reducing a source-body resistance.   
   
   
       11 . The trenched semiconductor power device of  claim 10  further comprising:
 a thick front metal layer disposed on top of said resistance-reduction layer for providing a contact layer for a wire or wireless bonding package.   
   
   
       12 . The trenched semiconductor power device of  claim 1  wherein:
 said trenched semiconductor power device further comprising a trenched MOSFET device.   
   
   
       13 . The trenched semiconductor power device of  claim 1  further comprising:
 a source-dopant region disposed below said source-body contact trench in direct contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of said epitaxial layer surrounding and below said body region supported on said semiconductor substrate.   
   
   
       14 . The trenched semiconductor power device of  claim 1  further comprising:
 a source-dopant region disposed below said source-body contact trench in direct contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of said epitaxial layer surrounding and below said body region supported on said semiconductor substrate.   
   
   
       15 . The trenched semiconductor power device of  claim 1  wherein:
 said trenched gate is filled with a dielectric material padded by a gate oxide layer with a bottom gate oxide layer significantly thicker than said gate oxide layer disposed along sidewalls of said trenched gate.   
   
   
       16 . The trenched semiconductor power device of  claim 1  further comprising:
 a source-dopant region disposed below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of said epitaxial layer surrounding and below said body region supported on said semiconductor substrate; and   said trenched gate is filled with a dielectric material padded by a gate oxide layer with a bottom gate oxide layer significantly thicker than said gate oxide layer disposed along sidewalls of said trenched gate.   
   
   
       17 . The trenched semiconductor power device of  claim 1  further comprising:
 a source-dopant region disposed below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of said epitaxial layer surrounding and below said body region supported on said semiconductor substrate; and   said trenched gate is filled with a dielectric material padded by a gate oxide layer with a bottom gate oxide layer significantly thicker than said gate oxide layer disposed along sidewalls of said trenched gate.   
   
   
       18 . A method for manufacturing a trenched semiconductor power device comprising a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, the method further comprising:
 covering said MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through said source and body regions and into an epitaxial layer below said body region for filling a contact metal plug therein; and forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of said source-body contact trench below said contact metal plug with said Schottky barrier layer having a barrier height for reducing a leakage current through said embedded Schottky diode during a reverse bias between said drain and said source.   
   
   
       19 . The method of  claim 18  further comprising a step of:
 forming a contact enhancement dopant region along a side wall of said source-body contact trench for improving an electrical contact of said contact metal plug to said body regions.   
   
   
       20 . The method of  claim 18  wherein:
 said step of forming said embedded Schottky diode further comprising a step of forming a CoSi2/ TiN barrier layer at a bottom surface of said source-body contact trench.   
   
   
       21 . The method of  claim 18  of  claim 1  wherein:
 said step of forming said embedded Schottky diode further comprising a step of forming a PtSi barrier layer at a bottom surface of said source-body contact trench.   
   
   
       22 . The method of  claim 18  further comprising:
 forming a source-dopant region below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of an epitaxial layer surrounding said body region supported on said semiconductor substrate.   
   
   
       23 . The method of  claim 18  further comprising:
 forming a source-dopant region below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of an epitaxial layer surrounding said body region supported on said semiconductor substrate.   
   
   
       24 . The method of  claim 18  further comprising:
 forming a source-dopant region below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of an epitaxial layer surrounding said body region supported on said semiconductor substrate; and   forming a gate insulation layer padded on sidewalls and a bottom surface of said trenched gate and filling said trenched gate with a dielectric material by with said gate insulation layer on said b&tom surface of said trenched gate significantly thicker than said gate insulation layer disposed along sidewalls of said trenched gate.   
   
   
       25 . The method of  claim 18  further comprising:
 forming a gate insulation layer padded on sidewalls and a bottom surface of said trenched gate and filling said trenched gate with a dielectric material by with said gate insulation layer on said bottom surface of said trenched gate significantly thicker than said gate insulation layer disposed along sidewalls of said trenched gate.   
   
   
       26 . The method of  claim 18  further comprising:
 forming a source-dopant region below said source-body contact trench in contact with said barrier layer of said Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of an epitaxial layer surrounding said body region supported on said semiconductor substrate; and   forming a gate insulation layer padded on sidewalls and a bottom surface of said trenched gate and filling said trenched gate with a dielectric material by with said gate insulation layer on said bottom surface of said trenched gate significantly thicker than said gate insulation layer disposed along sidewalls of said trenched gate.