Two-bit per i/o line write data bus for ddr1 and ddr2 operating modes in a dram

Abstract

A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

1 . An integrated circuit memory comprising:
 a data bus having a first end coupled to an I/O section and a second end coupled to a main memory interface;   circuitry at the second end of the data bus for receiving control signals based on a main chip clock to determine a first group of two data bits and a second group of two bits to be used for every given write address.   
   
   
       2 . The integrated circuit memory of  claim 1  further comprising circuitry for temporarily storing the first group of two data bits. 
   
   
       3 . The integrated circuit memory of  claim 2  further comprising circuitry for combining the first group with the second group to provide a four-bit data word driven on the memory bus. 
   
   
       4 . The integrated circuit memory of  claim 2  further comprising circuitry for allowing both DDR1 and DDR2 modes of operation.