Method For Polishing A Semiconductor Wafer And Polished Semiconductor Wafer Producible According To The Method

Abstract

Semiconductor wafers are polished between upper and lower polishing plates, the semiconductor wafer being polished on both sides while in a recess of a carrier by supplying a polishing agent. The wafer is double-side polished in a first polishing step, which is concluded with a negative overhang, defined as the difference between the thickness of the wafer and the thickness of the carrier after the first polishing step. The wafer is then double-side polished in a second polishing step, in which less than 1 μm of material is removed from the surfaces of the wafer. Silicon semiconductor wafers having polished front and rear sides with a front side global planarity SBIRmax value of less than 100 nm, and a front side local planarity PSFQR value of 35 nm or less in an edge region, with an edge exclusion of 2 mm, are obtained.

1 . A method for polishing a semiconductor wafer between an upper polishing plate and a lower polishing plate, the semiconductor wafer being polished on both sides while lying in a recess of a carrier by supplying a polishing agent, comprising:
 double-sided polishing of the semiconductor wafer in a first polishing step, which is concluded with a negative overhang, the overhang being the difference between the thickness of the semiconductor wafer and the thickness of the carrier after the first polishing step, and double-sided polishing of the semiconductor wafer in a second polishing step, in which less than 1 μm of material is polished from the side surfaces of the semiconductor wafer.   
     
     
         2 . The method of  claim 1 , wherein the first polishing step is concluded with a negative overhang of less than 0 μm, to −4 μm. 
     
     
         3 . The method of  claim 1 , wherein from 0.2 μm to less than 1 μm of material is polished from the side surfaces of the semiconductor wafer in the second polishing step. 
     
     
         4 . The method of  claim 2 , wherein from 0.2 μm to less than 1 μm of material is polished from the side surfaces of the semiconductor wafer in the second polishing step. 
     
     
         5 . The method of  claim 1 , wherein a concavity of the semiconductor wafer is measured after the first polishing step and the polishing abrasion carried in the second polishing step is made dependent on the measured concavity. 
     
     
         6 . The method of  claim 2 , wherein a concavity of the semiconductor wafer is measured after the first polishing step and the polishing abrasion carried in the second polishing step is made dependent on the measured concavity. 
     
     
         7 . The method of  claim 3 , wherein a concavity of the semiconductor wafer is measured after the first polishing step and the polishing abrasion carried in the second polishing step is made dependent on the measured concavity. 
     
     
         8 . The method of  claim 4 , wherein a concavity of the semiconductor wafer is measured after the first polishing step and the polishing abrasion carried in the second polishing step is made dependent on the measured concavity. 
     
     
         9 . The method of  claim 1 , wherein the overhang in the second polishing step is ≧0 μm. 
     
     
         10 . The method of  claim 1 , wherein the overhang in the second polishing step is from ≧0 μm to 2 μm. 
     
     
         11 . A silicon semiconductor wafer having a polished front side and a polished rear side with a front side global planarity expressed by an SBIRmax value of less than 100 nm, and with a front side local planarity expressed by a PSFQR value of 35 nm or less in an edge region, an edge exclusion of 2 mm being considered in each case. 
     
     
         12 . The semiconductor wafer of  claim 11 , having a diameter of 200 mm or 300 mm.