Method and system for sealing packages for optics

Abstract

A system for wafer-level packaging of a plurality of MEMS devices includes a substrate having a plurality of individual chips. Each of the plurality of individual chips includes a plurality of MEMS devices and each of the plurality of individual chips is arranged in a spatial manner as a first array configuration. The system also includes a transparent member of a predetermined thickness. The transparent member includes a transparent substrate of a first thickness having a bonding surface joined to a bonding surface of a standoff substrate of a second thickness. The standoff substrate defines a plurality of recessed regions arranged in a spatial manner as a second array configuration. The system further includes a sealed interface between the standoff substrate and the substrate. The sealed interface is adapted to enclose each of the plurality of individual chips within one of the plurality of recessed regions.

1 . A system for enclosing and individually sealing devices, the system comprising: 
 a substrate comprising a plurality of individual chips, wherein each of the plurality of individual chips includes a plurality of MEMS devices, the plurality of individual chips being formed in an array configuration with a first separation region extending in a first direction between each of the plurality of individual chips and a second separation region extending in a second direction between each of the plurality of individual chips, the first direction being oriented at an angle with respect to the second direction; and    a transparent member of a predetermined thickness, the transparent member comprising a transparent substrate of a first thickness having a bonding surface joined to a bonding surface of a standoff substrate of a second thickness, a sum of the first thickness and the second thickness being equal to the predetermined thickness, wherein the standoff substrate defines a plurality of recessed regions arranged in a spatial manner as a second array configuration; and    a sealed interface between the standoff substrate and the first separation region and the second separation region, wherein the sealed interface is adapted to enclose and individually seal each of the plurality of individual chips within one of the plurality of recessed regions.    
   
   
       2 . The system of  claim 1  wherein the first separation region comprises a plurality of first street regions arranged in strips and the second separation region comprises a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration.  
   
   
       3 . The system of  claim 1  wherein the standoff substrate comprises a second transparent member.  
   
   
       4 . The system of  claim 1  wherein the predetermined thickness of the transparent member ranges from about 0.5 mm to about 3.0 mm.  
   
   
       5 . The system of  claim 1  wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to about 1.0 mm.  
   
   
       6 . The system of  claim 1  wherein the transparent member further comprises a filter mask that forms an aperture region around a periphery of each of the plurality of individual chips, wherein the filter mask is disposed on a surface of the transparent member.  
   
   
       7 . The system of  claim 1  wherein the plurality of MEMS devices comprise micro-mirror structures and the substrate further comprises CMOS circuitry in electrical communication with the micro-mirror structures.  
   
   
       8 . The system of  claim 1  wherein each of the plurality of individual chips is maintained within an environment within the one of the plurality of recessed regions, wherein the environment comprises at least one of nitrogen, argon, or a mixture of nitrogen and argon.  
   
   
       9 . The system of  claim 1  wherein the bonding surface of the transparent substrate is coupled to the bonding surface of the standoff substrate by an epoxy seal.  
   
   
       10 . The system of  claim 9  wherein the sealed interface comprises an epoxy seal.  
   
   
       11 . A package for a plurality of MEMS devices, the package comprising: 
 a substrate including the plurality of MEMS devices, the substrate including a peripheral portion surrounding the plurality of MEMS devices;    a transparent member of a predetermined thickness, the transparent member comprising a transparent portion of a first thickness and a standoff portion of a second thickness and defining an annular structure, a sum of the first thickness and the second thickness being equal to the predetermined thickness, wherein a bonding surface of the transparent portion is coupled to a bonding surface of the standoff portion; and    a sealed interface between the annular structure of the standoff portion and the peripheral portion of the substrate, wherein the sealed interface is adapted to enclose and individually seal the plurality of MEMS devices within the transparent member.    
   
   
       12 . The package of  claim 11  wherein the transparent portion comprises a glass element.  
   
   
       13 . The package of  claim 12  wherein the predetermined thickness of the transparent member ranges from about 2.0 mm to about 3.0 mm, the standoff portion comprises a glass element, and the second thickness ranges from about 0.5 mm to about 1.0 mm.  
   
   
       14 . The package of  claim 11  wherein the bonding surface of the transparent portion is coupled to the bonding surface of the standoff portion by an epoxy seal.  
   
   
       15 . The package of  claim 14  wherein the sealed interface comprises an epoxy seal.  
   
   
       16 . The package of  claim 11  wherein the transparent member further comprises a filter mask registered to the annular structure, wherein the filter mask is disposed on a surface of the transparent member.  
   
   
       17 . The package of  claim 11  wherein the plurality of MEMS devices comprise micro-mirror structures and the substrate further comprises CMOS circuitry in electrical communication with the micro-mirror structures.  
   
   
       18 . A system for enclosing and sealing a plurality of MEMs devices, the system comprising: 
 a transparent member of a predetermined thickness, the transparent member comprising a transparent substrate of a first thickness having a bonding surface joined to a bonding surface of a standoff substrate of a second thickness, a sum of the first thickness and the second thickness being equal to the predetermined thickness, wherein the transparent member defines a plurality of recessed regions arranged in a spatial manner as an array configuration;    a die comprising the plurality of MEMS devices, the die including a first set of peripheral separation regions extending in a first direction and a second set of peripheral separation regions extending in a second direction, the first direction being oriented at an angle with respect to the second direction; and    a sealed interface between the standoff substrate and the first set of peripheral separation regions and the second set of peripheral separation regions, wherein the sealed interface is adapted to enclose and seal the plurality of MEMs devices within one of the plurality of recessed regions.    
   
   
       19 . The system of  claim 18  wherein the plurality of MEMS devices comprise micro-mirror structures and the die further comprises CMOS circuitry in electrical communication with the micro-mirror structures.  
   
   
       20 . The system of  claim 18  wherein the standoff substrate comprises a glass element and the second thickness ranges from about 0.1 mm to about 1.0 mm.  
   
   
       21 . The system of  claim 18  wherein the bonding surface of the transparent substrate is coupled to the bonding surface of the standoff substrate by an epoxy seal and the sealed interface comprises an epoxy seal.  
   
   
       22 . A system for enclosing and individually sealing one of a plurality of individual chips, the system comprising: 
 a substrate comprising a plurality of individual chips, wherein each of the plurality of individual chips includes a plurality of MEMS devices, the plurality of individual chips being formed in an array configuration with a first separation region extending in a first direction between each of the plurality of individual chips and a second separation region extending in a second direction between each of the plurality of individual chips, the first direction being oriented at an angle with respect to the second direction; and    a transparent member of a predetermined thickness, the transparent member comprising a transparent cover of a first thickness having a bonding surface joined to a bonding surface of an annular standoff member of a second thickness, a sum of the first thickness and the second thickness being equal to the predetermined thickness, wherein the transparent member defines a recessed region internal to the annular standoff member; and    a sealed interface between the annular standoff member and the plurality of first street regions and the plurality of second street regions, wherein the sealed interface is adapted to enclose and individually seal the one of the plurality of individual chips within the recessed region.    
   
   
       23 . The system of  claim 22  wherein the plurality of MEMS devices comprise micro-mirror structures and the substrate further comprises CMOS circuitry in electrical communication with the micro-mirror structures.  
   
   
       24 . The system of  claim 22  wherein the annular standoff member comprises a second transparent member and the second thickness ranges from about 0.1 mm to about 1.0 mm.  
   
   
       25 . The system of  claim 22  wherein the bonding surface of the transparent cover is coupled to the bonding surface of the annular standoff member by an epoxy seal and the sealed interface comprises an epoxy seal.