Methods of forming silicide regions and resulting MOS devices

Abstract

A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

1 . A semiconductor device comprising:
 a semiconductor substrate;   a gate stack comprising:
 a gate dielectric overlying the semiconductor substrate; and 
 a gate electrode overlying the gate dielectric; 
   a gate silicide region on the gate electrode;   a source/drain region adjacent the gate stack; and   a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.   
     
     
         2 . The semiconductor device of  claim 1 , wherein at least one metal is included in only one of the source/drain silicide region and the gate silicide region. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the source/drain silicide region has a higher thermal stability than the gate silicide region has. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the source/drain silicide region and the gate silicide region have substantially different thicknesses. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the source/drain silicide region is substantially free from nickel, and the gate silicide region is substantially free from cobalt. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the source/drain silicide region comprises cobalt as an only metallic element, and the gate silicide region comprises nickel as an only metallic element. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the source/drain silicide region has a substantially greater concentration of cobalt than does the gate silicide region. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the source/drain silicide region has a substantially smaller concentration of nickel than does the gate silicide region. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the source/drain silicide region comprises a metal selected from the group consisting essentially of cobalt, platinum, nickel, and combinations thereof, and the gate silicide region comprises a metallic material selected from the group consisting essentially of nickel, nickel-platinum, cobalt, and combinations thereof. 
     
     
         10 . A semiconductor device comprising:
 a semiconductor substrate having a channel region;   a gate dielectric on the substrate and over the channel region;   a gate silicide region over the gate dielectric;   a source/drain region adjacent the gate dielectric with the channel region therebetween; and   a source/drain silicide region on the source/drain region, wherein the source/drain silicide region has a roll-off resistivity at a higher dimension than does the gate silicide region.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the source/drain silicide region comprises silicides having a higher thermal stability than does the gate silicide region. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the source/drain silicide region comprises a metal selected from the group consisting essentially of cobalt, platinum, nickel, and combinations thereof, and wherein the gate silicide region comprises a metal selected from the group consisting essentially of nickel, nickel-platinum, cobalt, and combinations thereof. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the source/drain silicide region comprises cobalt, and wherein the gate silicide region comprises nickel. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the source/drain silicide region further comprises germanium. 
     
     
         15 . The semiconductor device of  claim 10 , wherein the gate silicide region is directly on the gate dielectric. 
     
     
         16 . The semiconductor device of  claim 10  further comprising a polysilicon region between the gate silicide region and the gate dielectric.