Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask

Abstract

Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

1 . A method for optimizing critical dimension, the method comprising:
 providing a first mask for an integrated circuit comprising at least one device region;   providing a second mask by copying the first mask; and   performing at least one lithography operation to the integrated circuit using the first mask and the second mask, wherein critical dimension of the integrated circuit is optimized using the second mask.   
   
   
       2 . The method of  claim 1 , wherein the second mask comprises a plurality of sacrificial patterns. 
   
   
       3 . The method of  claim 2 , wherein the plurality of sacrificial patterns is a plurality of flat patterns. 
   
   
       4 . The method of  claim 2 , wherein the plurality of sacrificial patterns is a plurality of grating patterns. 
   
   
       5 . The method of  claim 3 , wherein the plurality of flat patterns provide flat areas for irregular patterns at the at least one device region. 
   
   
       6 . The method of  claim 2 , wherein a sacrificial pattern in the plurality of sacrificial patterns has a dimension of about 3 um to about 70 um and are uniformly distributed over the second mask. 
   
   
       7 . The method of  claim 2 , wherein a spacing is present between the plurality of sacrificial patterns. 
   
   
       8 . The method of  claim 7 , wherein dimension of the spacing is substantially larger than dimension of a sacrificial pattern in the plurality of sacrificial patterns. 
   
   
       9 . The method of  claim 7 , wherein the spacing has a dimension of twice a dimension of a sacrificial pattern in the plurality of sacrificial patterns. 
   
   
       10 . The method of  claim 2 , wherein each of the plurality of sacrificial patterns has an area of about 9 um 2  to about 490 um 2 . 
   
   
       11 . The method of  claim 2 , wherein the plurality of sacrificial patterns are substantially symmetrical to each other. 
   
   
       12 . The method of  claim 3 , wherein the plurality of sacrificial patterns comprises a plurality of flat patterns and a plurality of grating patterns. 
   
   
       13 . The method of  claim 12 , wherein the critical dimension of the integrated circuit is optimized using the second mask comprises:
 determining critical dimension of a first layer using the plurality of grating patterns;   determining critical dimension of a second layer below the first layer using the plurality of flat patterns, wherein the plurality of flat patterns provide flat areas for a plurality of irregular patterns in the second layer; and   optimizing critical dimension of the integrated circuit based on the critical dimension of the first layer and the critical dimension of the second layer.   
   
   
       14 . The method of  claim 13 , wherein the first layer is an oxide domain layer, and wherein the second layer is a poly layer. 
   
   
       15 . The method of  claim 2 , wherein optimizing critical dimension of the integrated circuit using the second mask comprises:
 selecting a plurality of local sacrificial patterns from the plurality of sacrificial patterns;   determining critical dimension of the plurality of local sacrificial patterns; and   optimizing critical dimension of the integrated circuit using critical dimension of the plurality of local sacrificial patterns.   
   
   
       16 . The method of  claim 15 , wherein the plurality of local sacrificial patterns are located over the at least one device region. 
   
   
       17 . The method of  claim 16 , wherein the plurality of local sacrificial patterns are located outside of the at least one device region. 
   
   
       18 . A mask for optimizing critical dimension of an integrated circuit comprising:
 a plurality of grating patterns; and   a plurality of flat patterns, wherein the mask is a copy of a production mask for an integrated circuit comprising at least one device region.   
   
   
       19 . The mask of  claim 18 , wherein the plurality of flat patterns provide flat areas for irregular patterns in a second layer of the integrated circuit. 
   
   
       20 . The mask of  claim 19 , wherein the plurality of flat patterns overlap the at least one device region.