US2007281441A1PendingUtilityA1
Semiconductor substrate and process for producing it
Est. expiryNov 11, 2024(expired)· nominal 20-yr term from priority
H10P 14/3411H10P 14/3256H10P 14/3211H10P 14/2905H10P 14/36H10W 10/181H10P 90/1914H10D 86/01
51
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of periodically arranged cavities below the surface. The invention also relates to a process for producing this semiconductor substrate and to an sSOI wafer produced from this semiconductor substrate.
Claims
exact text as granted — not AI-modified1 .- 4 . (canceled)
5 . The process of claim 21 , comprising the following steps, in the order given:
a) producing a layer containing periodically arranged recesses at the surface of a single-crystal silicon wafer, and b) heat treating the single-crystal silicon wafer until a continuous layer consisting of single-crystal silicon has formed at the surface, with a layer of periodically arranged cavities beneath the surface, wherein after the heat treating, a single-crystal, relaxed layer with a thickness of from 5 nm to 3 μm, which contains silicon and germanium, is deposited on the continuous layer at the surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight.
6 . The process of claim 21 , comprising the following steps, in the order given:
c depositing a layer containing silicon and germanium on the surface of a single-crystal silicon wafer, the layer being from 5 nm to 3 μm thick and having a germanium content at the surface of the layer in the range from 10% by weight to 100% by weight, d producing a layer containing periodically arranged recesses at the surface of the single-crystal silicon wafer comprising the layer containing silicon and germanium, and e heat treating of the single-crystal silicon wafer until a continuous, single-crystal, relaxed layer containing silicon and germanium has formed at the surface, with a layer of periodically arranged cavities beneath the relaxed layer.
7 . The process of claim 5 , wherein a strained silicon layer is deposited on the surface of the layer containing silicon and germanium.
8 . The process of claim 6 , wherein a strained silicon layer is deposited on the surface of the layer containing silicon and germanium.
9 . The process of claim 7 , wherein the strained silicon layer is bonded to a handle wafer.
10 . The process of claim 8 , wherein the strained silicon layer is bonded to a handle wafer.
11 . The process of claim 9 , wherein the bonded wafers are split along the layer of cavities, so that the strained silicon layer and the layer containing silicon and germanium above it remain on the handle wafer.
12 . The process of claim 10 , wherein the bonded wafers are split along the layer of cavities, so that the strained silicon layer and the layer containing silicon and germanium above it remain on the handle wafer.
13 . The process of claim 11 , wherein the layer containing silicon and germanium is removed.
14 . The process of claim 12 , wherein the layer containing silicon and germanium is removed.
15 . The process of claim 5 , wherein the layer containing silicon and germanium is bonded to a handle wafer.
16 . The process of claim 6 , wherein the layer containing silicon and germanium is bonded to a handle wafer.
17 . The process of claim 15 , wherein the bonded wafers are split along the layer of cavities, so that the layer containing silicon and germanium remains on the handle wafer.
18 . The process of claim 16 , wherein the bonded wafers are split along the layer of cavities, so that the layer containing silicon and germanium remains on the handle wafer.
19 . The process of claim 17 , wherein a strained silicon layer is deposited on the surface of the layer containing silicon and germanium, which has remained on the handle wafer.
20 . The process of claim 18 , wherein a strained silicon layer is deposited on the surface of the layer containing silicon and germanium, which has remained on the handle wafer.
21 . A process for producing a semiconductor substrate comprising a continuous silicon and germanium layer above a single crystal silicon wafer and separated therefrom by a layer of periodically arranged cavities, comprising the following sequences of steps, in the order given:
a) producing a layer containing periodically arranged recesses at the surface of a single-crystal silicon wafer, and b) heat treating the single-crystal silicon wafer until a continuous layer consisting of single-crystal silicon has formed at the surface, with a layer of periodically arranged cavities beneath the surface, wherein after the heat treating, a single-crystal, relaxed layer with a thickness of from 5 nm to 3 μm, which contains silicon and germanium, is deposited on the continuous layer at the surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight; or c) depositing a layer containing silicon and germanium on the surface of a single-crystal silicon wafer, the layer being from 5 nm to 3 μm thick and having a germanium content at the surface of the layer in the range from 10% by weight to 100% by weight, d) producing a layer containing periodically arranged recesses at the surface of the single-crystal silicon wafer comprising the layer containing silicon and germanium, and e) heat treating of the single-crystal silicon wafer until a continuous, single-crystal, relaxed layer containing silicon and germanium has formed at the surface, with a layer of periodically arranged cavities beneath the relaxed layer.Join the waitlist — get patent alerts
Track US2007281441A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.