IC chip package with minimized packaged-volume

Abstract

An IC chip package, including a single chip package, two stacked chips package or a System-In-Package (SIP), is created to minimize the assembled volume, which basic structure comprises a chip, a circuited substrate provided for the chip electrically mounted thereon and an encapsulated means for covering the chip to constitute a package structure, wherein the chip has a processed substrate with an active side and an inactive side and one or more half-tunneling electrical contacts penetrating the processed substrate to form one or more electrical contacts on the inactive side of the chip, so that the chip is directly through the inactive side of the processed substrate electrically mounted to the circuited substrate without via bonding wires.

1 . An IC chip package at least comprises a chip, a circuited substrate having a top and bottom surfaces on which conductive circuit patterns formed with electrical contacts respectively laid-out for providing the chip electrically mounted thereon, and an encapsulated means for covering the chip to constitute a package structure, characterized in that the chip has a processed substrate with an active side and an inactive side and one or more half-tunneling electrical contacts penetrating the processed substrate, wherein each half-tunneling electrical contact of the chip has a first end exposed on the inactive side of the processed substrate and formed as an electrical contact on the inactive side of the chip and a second end exposed on the active side of the processed substrate and electrically connected to a circuit formed inside the chip. 
   
   
       2 . The IC chip package as described in  claim 1 , wherein the electrical contacts on the inactive side of the chip are electrically connected to the corresponding electrical contacts of the circuited substrate without via bonding wires. 
   
   
       3 . The IC chip package as described in  claim 1 , wherein on the active side of the chip has one or more electrical contacts which are electrically connected to the corresponding electrical contacts of the circuited substrate without via bonding wires. 
   
   
       4 . The IC chip package as described in  claim 2 , further comprising a circuited substrate for providing the chip electrically mounted thereon, and on the active side of the chip has one or more electrical contacts which are electrically connected to the corresponding electrical contacts of the circuited substrate without via bonding wires. 
   
   
       5 . The IC chip package as described in  claim 2 , wherein on the active side of the chip has one or more electrical contacts which are via bonding wires electrically connected to the corresponding electrical contacts of the circuited substrate. 
   
   
       6 . The IC chip package as described in  claim 2 , further comprising an electronic element or a transparent material is installed over the chip and the circuited substrate. 
   
   
       7 . The IC chip package as described in  claim 6 , wherein the chip is formed with one or more electro-optical elements. 
   
   
       8 . The IC chip package as described in  claim 7 , wherein the electro-optical element formed on the chip is a pressure sensor element or a temperature sensor element. 
   
   
       9 . An IC chip package at least comprises two stacked chips, a circuited substrate having a top and bottom surfaces on which conductive circuit patterns formed with electrical contacts respectively laid-out for providing the lowermost chip electrically mounted thereon, and an encapsulated means for covering the stacked chips to constitute a package structure, characterized in that each chip has a processed substrate with an active side and an inactive side and one or more half-tunneling electrical contacts penetrating the processed substrate for forming one or more electrical contacts on both inactive side and active side of the chip, wherein one or more electrical contacts formed on the inactive side of the topmost chip are electrically connected to the corresponding electrical contact(s) formed on the active side of the lowermost chip, and wherein the electrical contacts formed on the inactive side of the lowermost chip are electrically connected to the corresponding electrical contacts of the circuited substrate without via bonding wires. 
   
   
       10 . The IC chip package as described in  claim 9 , wherein the two chips are stacked together in parallel electrical connection without via bonding wires. 
   
   
       11 . The IC chip package as described in  claim 9 , wherein the two chips are stacked together in serial electrical connection without via bonding wires. 
   
   
       12 . An IC chip package at least comprises a first chip provided for one or more second chips or electronic components electrically connected thereon for packaging a System-In-Package, a circuited substrate having a top and bottom surfaces on which conductive circuit patterns formed with electrical contacts respectively laid-out for providing the first chip electrically mounted thereon, and an encapsulated means for covering the first chips and the second chip(s) and/or the electronic component(s) to constitute a SIP package structure, characterized in that each chip has a processed substrate with an active side and an inactive side and one or more half-tunneling electrical contacts penetrating the processed substrate for forming one or more electrical contacts on both inactive side and active side of the chip, wherein the electrical contacts on the inactive side of the second chip(s) is electrically connected to the electrical contacts on the active side of the first chip, and wherein the electrical contacts formed on the inactive side of the first chip are electrically connected to the corresponding electrical contacts of the circuited substrate without via bonding wires. 
   
   
       13 . The IC chip package as described in  claim 12 , wherein the first chip is a CPU and the second chip(s) is a memory chip. 
   
   
       14 . The IC chip package as described in  claim 12 , wherein both the first chip and the second chip(s) are memory chips. 
   
   
       15 . The IC chip package as described in  claim 13 , wherein the electronic component is a resistor or a capacitor.