US2007235852A1PendingUtilityA1

Method and system for sealing packages for optics

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Assignee: MIRADIA INCPriority: Oct 24, 2003Filed: Jun 14, 2007Published: Oct 11, 2007
Est. expiryOct 24, 2023(expired)· nominal 20-yr term from priority
Inventors:Xiao YangDongmin Chen
H10W 90/754H10W 74/00H10W 72/5522H10W 76/18H10W 95/00H10W 76/10H10F 77/50H10F 39/8053H10F 39/804H10F 99/00G02B 26/0833Y10T156/1092Y10T156/1093
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Claims

Abstract

A system for wafer-level packaging of a plurality of MEMS devices includes a substrate having a plurality of individual chips. Each of the plurality of individual chips includes a plurality of MEMS devices and each of the plurality of individual chips is arranged in a spatial manner as a first array configuration. The system also includes a transparent member of a predetermined thickness. The transparent member includes a transparent substrate of a first thickness having a bonding surface joined to a bonding surface of a standoff substrate of a second thickness. The standoff substrate defines a plurality of recessed regions arranged in a spatial manner as a second array configuration. The system further includes a sealed interface between the standoff substrate and the substrate. The sealed interface is adapted to enclose each of the plurality of individual chips within one of the plurality of recessed regions.

Claims

exact text as granted — not AI-modified
1 . A system for wafer-level packaging of a plurality of MEMS devices, the system comprising: 
 a substrate comprising a plurality of MEMS devices, wherein the plurality of MEMS devices are arranged in a spatial manner as a first array configuration;    a cover substrate of a predetermined thickness, the cover substrate comprising: 
 a plurality of recessed regions having a height less than the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array configuration registered to the first array configuration; and  
 standoff regions of the predetermined thickness surrounding the plurality of recessed regions, the standoff regions having a bonding surface; and  
   a sealed interface between the bonding surface of the standoff regions and the substrate, wherein the sealed interface is configured to enclose and individually seal each of the plurality of MEMS devices within one of the plurality of recessed regions.    
   
   
       2 . The system of  claim 1  wherein the first array configuration includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the first array configuration.  
   
   
       3 . The system of  claim 2  wherein the bonding surface of the standoff regions is joined to the plurality of first street regions and the plurality of second street regions.  
   
   
       4 . The system of  claim 1  wherein the sealed interface comprises a covalent bond interface or a eutectic bond interface.  
   
   
       5 . The system of  claim 1  wherein the cover substrate comprises a silicon member.  
   
   
       6 . The system of  claim 1  wherein the plurality of MEMS devices comprise a plurality of polysilicon devices.  
   
   
       7 . The system of  claim 1  wherein the predetermined thickness of the cover substrate ranges from about 0.5 mm to about 3.0 mm.  
   
   
       8 . The system of  claim 7  wherein the predetermined thickness of the cover substrate ranges from about 2.0 mm to about 3.0 mm.  
   
   
       9 . The system of  claim 1  wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to about 1.0 mm.  
   
   
       10 . The system of  claim 9  wherein the depth of each of the plurality of recessed regions ranges from about 0.5 mm to about 1.0 mm.  
   
   
       11 . The system of  claim 1  wherein each of the plurality of MEMS devices is maintained within an inert environment within the one of the plurality of recessed regions.  
   
   
       12 . The system of  claim 11  wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.  
   
   
       13 . The system of  claim 1  wherein the substrate comprises a silicon bearing material.  
   
   
       14 . The system of  claim 1  wherein the substrate comprises CMOS circuitry.  
   
   
       15 . The system of  claim 1  wherein the plurality of MEMS devices comprise deflection devices.  
   
   
       16 . A method of wafer-level packaging a plurality of MEMS devices, the method comprising: 
 providing a substrate comprising a plurality of MEMS devices, wherein the plurality of MEMS devices are arranged in a spatial manner as a first array configuration;    providing a cover substrate of a predetermined thickness, the cover substrate comprising: 
 a plurality of recessed regions having a height less than the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array configuration registered to the first array configuration; and  
 standoff regions of the predetermined thickness surrounding the plurality of recessed regions, the standoff regions having a bonding surface; and  
   bonding the bonding surface of the standoff regions to the substrate to form a sealed interface, wherein the sealed interface is configured to enclose and individually seal each of the plurality of MEMS devices within one of the plurality of recessed regions.    
   
   
       17 . The method of  claim 16  wherein the first array configuration includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the first array configuration.  
   
   
       18 . The method of  claim 17  wherein bonding the bonding surface of the standoff regions to the substrate to form a sealed interface comprises joining the bonding surface of the standoff regions to the plurality of first street regions and the plurality of second street regions.  
   
   
       19 . The method of  claim 16  wherein bonding the bonding surface of the standoff regions to the substrate to form a sealed interface comprises performing at least one of a covalent bonding process or a eutectic bonding process.  
   
   
       20 . The method of  claim 16  wherein the cover substrate comprises a silicon member.  
   
   
       21 . The method of  claim 16  wherein the plurality of MEMS devices comprise a plurality of polysilicon devices.  
   
   
       22 . The method of  claim 16  wherein the predetermined thickness of the cover substrate ranges from about 0.5 mm to about 3.0 mm.  
   
   
       23 . The method of  claim 16  wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to about 1.0 mm.  
   
   
       24 . The method of  claim 16  wherein each of the plurality of MEMS devices is maintained within an inert environment within the one of the plurality of recessed regions.  
   
   
       25 . The method of  claim 24  wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.  
   
   
       26 . The method of  claim 16  wherein the substrate comprises a silicon bearing material.  
   
   
       27 . The method of  claim 16  wherein the substrate comprises CMOS circuitry.  
   
   
       28 . The system of  claim 16  wherein the plurality of MEMS devices comprise deflection devices.

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