Novel architecture to monitor isolation integrity between floating gate and source line

Abstract

A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

1 . A floating gate isolation test structure comprising: 
 a substrate;    a gate oxide layer overlying said substrate;    a floating gate conductor layer overlying said gate oxide layer;    source regions in said substrate;    contacting structures to said source regions; and    contacting structures to said floating gate conductor layer.    
   
   
       2 . The test structure according to  claim 1  wherein said contacting structures to said source regions further comprise a conductive plug overlying said source region.  
   
   
       3 . The test structure according to  claim 1  wherein said substrate comprises a monitoring wafer processed along with product wafers.  
   
   
       4 . The test structure according to  claim 1  wherein conductive types of said floating gate conductor layer and said substrate are different.  
   
   
       5 . The test structure according to  claim 1  wherein a voltage is applied between said floating gate conductor layer and said substrate, and a current passes through said floating gate conductor layer.  
   
   
       6 . The test structure according to  claim 5  wherein said floating gate conductor layer is shorted to said source region if said current is greater than about 25 μAmps.  
   
   
       7 . The test structure according to  claim 5  wherein said floating gate conductor layer is shorted to said substrate is said current is greater than about 15 μAmps.  
   
   
       8 . The test structure according to  claim 1  further comprising: 
 a plurality of spacers on sidewalls of said floating gate conductor layer;    a second conductor layer overlying said source region; and    a conductive plug overlying said source region.    
   
   
       9 . The test structure according to  claim 1  further comprising: 
 a dielectric layer with contact openings overlying said floating gate conductor layer; and    a second conductor layer overlying said floating gate conductor layer and said dielectric layer, wherein said second conductor layer is patterned to form the conductive lines.