US2007166876A1PendingUtilityA1

Components, methods and assemblies for multi-chip packages

Assignee: TESSERA INCPriority: Oct 11, 2002Filed: Jan 3, 2006Published: Jul 19, 2007
Est. expiryOct 11, 2022(expired)· nominal 20-yr term from priority
H05K 3/3436H05K 1/141H05K 2203/1572H05K 2201/10719H10W 90/724H10W 90/722H10W 90/20H10W 72/9415H10W 72/90H10W 70/60H10W 90/00H10W 72/00H10D 64/00
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Claims

Abstract

An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Claims

exact text as granted — not AI-modified
1 . A method for mounting a warped multi-chip module to a circuit board, the method comprising the steps of: 
 positioning a warped multi-chip module over a circuit board for mounting thereto; and    raising a temperature of the warped multi-chip module to a temperature such that the warped multi-chip module relatively flattens and mounting masses reflow for electrically and mechanically bonding the now relatively flat multi-chip module to the circuit board.    
   
   
       2 . The method of  claim 1  wherein the mounting masses are initially attached to a surface of the multi-chip module before reflow for bonding to the circuit board.  
   
   
       3 . The method of  claim 1  wherein the warped multi-chip module comprises no underfill material.  
   
   
       4 . The method of  claim 1  further comprising the following steps prior to the positioning step: 
 testing packaged semiconductor chips of the warped multi-chip module;    if a tested packaged semiconductor chip fails, replacing the failed packaged semiconductor chip with another packaged semiconductor chip of the same type.    
   
   
       5 . The method of  claim 1  further comprising the following steps prior to the positioning step: 
 forming the warped multi-chip module by using land grid array (LGA) connections for at least one packaged semiconductor chip on a top surface of an interposer and by using LGA connections for at least one packaged semiconductor chip on a bottom surface of the interposer such that the packaged semiconductors chips are removably connected to the interposer.

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