Method for forming a copper metal interconnection of a semiconductor device

Abstract

Embodiments relate to a method for forming a copper metal interconnection of a semiconductor device. In embodiments, a copper metal interconnection may be formed through a damascene process. The method may include forming a first copper plating layer on an interlayer dielectric layer of the semiconductor substrate by performing an electrical-chemical plating scheme with a first plating distance, measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance according to the surface uniformity of the first copper plating layer.

1 . A method comprising: 
 forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate in a plating tank through an electrical-chemical plating process while maintaining a plating distance at a first plating distance;    determining existence of a concave part by measuring surface uniformity of the first copper plating layer; and    forming a second copper plating layer on the first copper plating layer by adjusting the plating distance to a second plating distance in the plating tank if the concave part exists in the first copper plating layer.    
   
   
       2 . The method of  claim 1 , wherein the second plating distance is less than the first plating distance if the concave part exists at a center part of the semiconductor substrate.  
   
   
       3 . The method of  claim 1 , wherein the second plating distance is less than the first plating distance if a thickness of a center part of the semiconductor substrate is less than a thickness at an edge of the semiconductor substrate after forming only the first copper plating layer.  
   
   
       4 . The method of  claim 1 , wherein the second plating distance is greater than the first plating distance if the concave part exists at an edge part of the semiconductor substrate.  
   
   
       5 . The method of  claim 1 , wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the semiconductor substrate is greater than a thickness at an edge of the semiconductor substrate after forming only the first copper plating layer.  
   
   
       6 . The method of  claim 1 , wherein the plating distance comprises a distance between an anode and the semiconductor substrate arranged in the plating tank.  
   
   
       7 . A method comprising: 
 forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate by performing an electrical-chemical plating process at a first plating distance;    forming a second copper plating layer on the first copper plating layer by performing the electrical-chemical plating process at a second plating distance according to a surface uniformity of the first copper plating layer.    
   
   
       8 . The method of  claim 7 , further comprising measuring the surface uniformity of the first copper plating layer.  
   
   
       9 . The method of  claim 7 , wherein the second plating distance is shorter than the first plating distance if a concave part exists at a center part of the first copper plating layer.  
   
   
       10 . The method of  claim 7 , wherein the second plating distance is less than the first plating distance if a thickness of a center part of the first copper plating layer is less than a thickness at an edge of the first copper plating layer.  
   
   
       11 . The method of  claim 7 , wherein the second plating distance is longer than the first plating distance if a concave part exists at an edge part of the first copper plating layer.  
   
   
       12 . The method of  claim 7 , wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the first copper plating layer is greater than a thickness at an edge of the first copper plating layer.  
   
   
       13 . The method of  claim 7 , wherein the plating distance comprises a distance between an anode and the semiconductor substrate arranged in the plating tank.  
   
   
       14 . A device, comprising: 
 an interlayer dielectric layer formed over a semiconductor substrate; and    a copper layer formed over the interlayer dielectric layer,    wherein the copper layer is formed by forming a first copper plating layer over the interlayer dielectric layer by performing an electrical-chemical plating process at a first plating distance and forming a second copper plating layer on the first copper plating layer by performing the electrical-chemical plating process at a second plating distance according to a surface uniformity of the first copper plating layer.    
   
   
       15 . The device of  claim 14 , wherein the second plating distance is less than the first plating distance if a thickness of a center part of the first copper plating layer is less than a thickness at an edge of the first copper plating layer.  
   
   
       16 . The method of  claim 15 , wherein a surface of the copper layer formed over the interlayer dielectric layer is substantially uniform in thickness.  
   
   
       17 . The method of  claim 14 , wherein the second plating distance is greater than the first plating distance if a thickness of a center part of the first copper plating layer is greater than a thickness at an edge of the first copper plating layer.  
   
   
       18 . The method of  claim 17 , wherein a surface of the copper layer formed over the interlayer dielectric layer is substantially uniform in thickness.