Back-face and edge interconnects for lidded package

Abstract

A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

1 . A microelectronic unit including: 
 (a) a chip with an upwardly-facing front surface, a downwardly-facing rear surface and one or more edges extending between said front and rear surfaces;    (b) a lid overlying at least a portion of the front surface of the chip, said lid having a top surface facing upwardly away from the chip, a bottom surface facing toward said chip and edges extending between said top and bottom surfaces; and    (c) edge unit connections exposed at one or more of said edges.    
     
     
         2 . The unit as claimed in  claim 1  further comprising vertical interconnect structures electrically connected to said chip and extending upwardly through said lid, at least some of said vertical interconnect structures being exposed at said one or more of said edges of said lid so that the exposed vertical interconnect structures define said edge unit connections.  
     
     
         3 . The unit as claimed in  claim 1  wherein said lid is sealed to said chip.  
     
     
         4 . The unit as claimed in  claim 1  wherein at least a part of said bottom surface of said lid is spaced from the front surface of said chip so that said lid and said chip cooperatively define an interior space within said unit.  
     
     
         5 . The unit as claimed in  claim 4  wherein said chip includes one or more elements selected from the group consisting of microelectromechanical elements, acoustically active elements and optoelectronic elements.