Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same

Abstract

A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.

1 . A SONOS gate structure, comprising: 
 a gate pattern with sidewalls on a substrate, wherein said gate pattern comprises a gate dielectric layer and a gate electrode;    an oxide structure on said substrate and said sidewalls of said gate pattern, wherein said oxide structure comprises a relatively thinner oxide portion on said substrate and a relatively thicker oxide portion on one of said sidewalls of said gate pattern; and    trapping dielectric spacers on said oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.    
   
   
       2 . The SONOS gate structure of  claim 1 , wherein said relatively thinner oxide portion has a thickness less than or equal to about 60 Angstroms.  
   
   
       3 . The SONOS gate structure of  claim 1 , wherein said relatively thicker oxide portion has a thickness greater than or equal to about 70 Angstroms.  
   
   
       4 . The SONOS gate structure of  claim 1 , wherein said oxide structure comprises silicon oxide.  
   
   
       5 . The SONOS gate structure of  claim 1 , wherein said trapping dielectric spacers comprise silicon nitride.  
   
   
       6 . A method of forming a SONOS gate structure, comprising: 
 forming a gate pattern with sidewalls on a substrate, wherein said gate pattern comprises a gate dielectric layer patterned on said substrate and a gate electrode patterned on said gate dielectric layer;    forming a first oxide layer on said gate pattern and said substrate;    etching back said first oxide layer to expose said substrate and the top of said gate electrode, leaving oxide spacers along said sidewalls of said gate pattern respectively;    forming a second oxide layer on said substrate and said oxide spacers, wherein said second oxide layer on said substrate is a relatively thinner oxide portion, and a combination of said oxide spacer and said second oxide layer along one of said sidewalls of said gate pattern is a relatively thicker oxide portion; and    forming trapping dielectric spacers on said second oxide layer adjacent to said sidewalls of said gate pattern respectively.    
   
   
       7 . The method of forming a SONOS gate structure of  claim 6 , wherein said relatively thinner oxide portion has a thickness about 20˜60 Angstroms.  
   
   
       8 . The method of forming a SONOS gate structure of  claim 6 , wherein said relatively thicker oxide portion has a thickness about 70˜200 Angstroms.  
   
   
       9 . The method of forming a SONOS gate structure of  claim 6 , wherein said first oxide layer and said second oxide layer are formed of silicon oxide.  
   
   
       10 . The method of forming a SONOS gate structure of  claim 6 , wherein said trapping dielectric spacers are formed of silicon nitride.  
   
   
       11 . The method of forming a SONOS gate structure of  claim 6 , further comprising implanting ions into said substrate to form source/drain regions using said trapping dielectric spacers as an implantation mask.  
   
   
       12 . A method of forming a SONOS gate structure, comprising: 
 forming a gate pattern with sidewalls on a substrate, wherein said gate pattern comprises a gate dielectric layer patterned on said substrate and a gate electrode patterned on said gate dielectric layer;    forming a first oxide layer on said gate pattern and said substrate;    forming a first dielectric layer on said first oxide layer;    etching back said first dielectric layer to expose said first oxide layer, leaving first dielectric spacers on said first oxide layer adjacent to said sidewalls of said gate pattern respectively;    etching back said first oxide layer and said first dielectric spacers to expose said substrate and the top of said gate electrode, leaving oxide spacers along said sidewalls of said gate pattern respectively, and leaving said first dielectric spacers on said oxide spacers respectively;    forming a second oxide layer on the exposed portions of said substrate, said gate electrode and said oxide spacers;    forming a second dielectric layer on said first dielectric spacers and said second oxide layer; and    etching back said second dielectric layer to expose said second oxide layer, leaving second dielectric spacers adjacent to said sidewalls of said gate pattern respectively.    
   
   
       13 . The method of forming a SONOS gate structure of  claim 12 , wherein said second oxide layer on said substrate is a relatively thinner oxide portion, and said oxide spacer along said sidewall of said gate pattern is a relatively thicker oxide portion  
   
   
       14 . The method of forming a SONOS gate structure of  claim 13 , wherein said relatively thinner oxide portion has a thickness about 20˜60 Angstroms.  
   
   
       15 . The method of forming a SONOS gate structure of  claim 13 , wherein said relatively thicker oxide portion has a thickness about 70˜200 Angstroms.  
   
   
       16 . The method of forming a SONOS gate structure of  claim 12 , wherein said first oxide layer and said second oxide layer are formed of silicon oxide.  
   
   
       17 . The method of forming a SONOS gate structure of  claim 12 , wherein a combination of said first dielectric spacer and said second dielectric spacer along one of said sidewalls of said gate pattern serves as a trapping dielectric spacer.  
   
   
       18 . The method of forming a SONOS gate structure of  claim 18 , wherein said first dielectric layer and said second dielectric layer are formed of silicon nitride.  
   
   
       19 . The method of forming a SONOS gate structure of  claim 17 , further comprising implanting ions into said substrate to form source/drain regions using said trapping dielectric spacers as an implantation mask.  
   
   
       20 . The method of forming a SONOS gate structure of  claim 12 , wherein said second oxide layer is selectively grown on the exposed portions of said substrate, said gate electrode and said oxide spacers through a thermal oxidation process.