Split gate flash devices

Abstract

A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.

1 . A split-gate flash device having a plurality of active regions and isolation regions, the device comprising: 
 a plurality of trenches in a semiconductor substrate, wherein the trenches are filled with an isolation layer;    a patterned conductor layer formed over a patterned dielectric layer of the substrate;    a notch profile formed at outer surface areas between the conductor layer and the dielectric layer; and    a portion of the isolation layer formed in the notch profile.    
   
   
       2 . The device of  claim 1 , wherein the patterned dielectric layer comprises oxide.  
   
   
       3 . The device of  claim 1 , wherein the patterned conductor layer comprises polysilicon.  
   
   
       4 . The device of  claim 1 , wherein the patterned dielectric layer has a thickness of between about 40 Å to 150 Å.  
   
   
       5 . The device of  claim 1 , wherein the isolation layer comprises a dielectric material.  
   
   
       6 . The device of  claim 1 , wherein the isolation layer has at least one extending edge covering at least one edge of the pattered dielectric layer.