MIM capacitor integrated into the damascene structure and method of making thereof

Abstract

This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.

1 . A semiconductor device, comprising: 
 a first damascene interconnect structure comprising: 
 a conductive via formed through a first interlevel dielectric layer and a first dielectric etch stop layer located under the first interlevel dielectric layer, wherein the conductive via contacts a first interconnect structure located under the first dielectric etch stop layer;  
 a conductive trench formed through a second interlevel dielectric layer and a second dielectric etch stop layer located between the first and second interlevel dielectric layers, wherein the conductive trench contacts the conductive via; and  
   a metal-insulator-metal capacitor comprising: 
 a first plate electrode formed on a second interconnect structure located under the first dielectric etch stop layer;  
 a second plate electrode formed on the first dielectric etch stop layer and substantially overlapping the first plate electrode;  
 a second damascene interconnect structure formed through the first and second interlevel dielectric layers and the first dielectric etch stop layer and contacting the second plate electrode.  
   
   
   
       2 . The semiconductor device of  claim 1 , wherein the first and second plate electrodes comprise a diffusion barrier.  
   
   
       3 . The semiconductor device of  claim 2 , wherein the diffusion barrier comprises a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the first interlevel dielectric layer and the second interlevel dielectric layer comprise a material selected from the group consisting essentially of silicon oxide, silicon nitride, silicon carbide, organo silicate glass (OSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), a porous oxides, polyarylene ether, hydrogen silesquioxane (HSQ), methyl silsesquioxane (MSQ), polysilsequioxane, polyimide, benzocyclbbutene, and combinations thereof.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the first and second damascene interconnect structures are dual damascene interconnect structures.  
   
   
       6 . The semiconductor device of  claim 1  further comprising: 
 a barrier liner between the first damascene interconnect structures and the first and second interlevel dielectric layers.    
   
   
       7 . The semiconductor device of  claim 6 , wherein the barrier liner comprises a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       8 . The integrated capacitor of  claim 1 , wherein the first capacitor electrode and the second capacitor electrode have a maximum dimension greater than or equal to a maximum lateral damascene trench dimension.  
   
   
       9 . A semiconductor device, comprising: 
 a first interlevel conductive via formed through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric layer and contacting a first interconnect structure located under the dielectric etch stop layer; and    a metal-insulator-metal capacitor comprising: 
 a first electrode formed on a second interconnect structure, the second interconnect structure located under the dielectric etch stop layer;  
 a second electrode formed on the dielectric etch stop layer, the second plate electrode being substantially parallel to the first plate electrode and substantially overlapping the first plate electrode;  
 a second interlevel conductive via formed through the interlevel dielectric layer and contacting the second electrode.  
   
   
   
       10 . The semiconductor device of  claim 9 , wherein the first and second electrodes comprise a diffusion barrier.  
   
   
       11 . The semiconductor device of  claim 10 , wherein the diffusion barrier comprises a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       12 . The semiconductor device of  claim 9 , wherein the first and second interlevel conductive vias further include a barrier liner.  
   
   
       13 . The semiconductor device of  claim 12 , wherein the barrier liner comprises a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       14 . The integrated capacitor of  claim 9 , wherein the first capacitor electrode and the second capacitor electrode have a maximum dimension greater than or equal to a maximum lateral second interlevel conductive via dimension.  
   
   
       15 . The semiconductor device of  claim 9 , wherein the first interlevel dielectric layer and the second interlevel dielectric layer comprise a material selected from the group consisting essentially of silicon oxide, silicon nitride, silicon carbide, organo silicate glass (OSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), a porous oxides, polyarylene ether, hydrogen silesquioxane (HSQ), methyl silsesquioxane (MSQ), polysilsequioxane, polyimide, benzocyclbbutene, and combinations thereof.  
   
   
       16 . A method of fabricating a damascene metal-insulator-metal capacitor, the method comprising: 
 providing a substrate, the substrate including a first conductive interconnect structure and a second conductive interconnect structure;    depositing a first layer of diffusion barrier material over the substrate;    patterning the first layer of diffusion barrier material to form a first capacitor electrode over the second interconnect structure;    forming a first dielectric etch stop layer over the substrate and over the first capacitor electrode;    forming a second layer of diffusion barrier material over the first dielectric etch stop layer;    patterning the second layer of diffusion barrier material to form a second capacitor electrode located substantially directly above the first capacitor electrode;    forming a first interlevel dielectric layer over the first dielectric etch stop layer and over the second capacitor electrode;    forming a second dielectric etch stop layer over the first interlevel dielectric layer;    forming a second interlevel dielectric layer over the second dielectric etch stop layer;    forming a first damascene interconnect structure through the first and second interlevel dielectric layers, the second dielectric etch stop layer, and contacting the second capacitor electrode; and    forming a second damascene interconnect structure through the first and second interlevel dielectric layers, the first and second dielectric etch stop layers and contacting the first conductive interconnect structure.    
   
   
       17 . The semiconductor device of  claim 16 , wherein the first layer of diffusion barrier material and the second layer of diffusion barrier material comprise a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       18 . The semiconductor device of  claim 16 , wherein forming the first and second damascene interconnect structures further includes a depositing barrier liner.  
   
   
       19 . The semiconductor device of  claim 18 , wherein the barrier liner comprises a material selected from the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       20 . The integrated capacitor of  claim 16 , wherein the first capacitor electrode and the second capacitor electrode have a maximum dimension greater than or equal to a maximum lateral damascene trench dimension.