Method for testing semiconductor devices and an apparatus therefor

Abstract

A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

1 . A test handler system for use with integrated circuit devices and with a plurality of test boards, each test board having a plurality of sockets, the individual ones of said plurality of sockets adapted to receive individual integrated circuit devices said test handler system comprising: 
 an input mechanism for providing a plurality of integrated circuit devices to be tested;    an individual tester for electrically testing individual integrated circuit devices, the individual tester having at least one test socket adapted to receive an integrated circuit device and to electrically connect the integrated circuit device with test electronics;    a pick-and-place apparatus configured to transfer integrated circuit devices from said input tray to i) said individual tester and then from said individual tester to sockets in a test board or (ii) to sockets in a test board without engaging the integrated circuit device in a test socket of said individual tester; and    a controller for unloading those integrated circuit devices populated into said sockets that failed the test at the individual tester.    
   
   
       2 . The test handler system of  claim 1  the controller further comprising a first signal generator that generates a signal indicative of a failed test, a memory that associates the failed test to the socket in which the device that failed the test is placed and a second signal generator that sends an instruction to said pick-and-place mechanism to removes said integrated circuit device that failed said test from its associated socket.