Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations

Abstract

An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.

1 . A memory circuit having one or more devices having substantially similar physical gate dielectric thicknesses but different electrical gate dielectric thicknesses, the memory circuit comprising: 
 a first device comprising: 
 a first gate dielectric layer, having a first physical gate dielectric thickness, formed on a substrate;  
 a first gate electrode, having a first dopant concentration, formed atop the first gate dielectric layer;  
   a second device comprising: 
 a second gate dielectric layer, having a second physical gate dielectric thickness, formed on the substrate;  
 a second gate electrode, having a second dopant concentration, formed atop the second gate dielectric layer,  
   wherein the first physical gate dielectric thickness is substantially the same as the second physical gate dielectric thickness, and the first dopant concentration is made substantially greater than the second dopant concentration by at least one predetermined doping process after the first device has undergone a prior doping process with the second device to cause the first physical gate dielectric thickness to be thinner than the second physical gate dielectric thickness by no less than two Angstroms.    
     
     
         2 . The memory circuit of  claim 1  wherein the second physical gate dielectric thickness is at least 5 Angstroms greater than the first physical gate dielectric thickness.  
     
     
         3 . The memory circuit of  claim 1  wherein the first and second device have sub-micron channel lengths.  
     
     
         4 . The memory circuit of  claim 1  wherein the first physical gate dielectric thickness and the second physical gate dielectric thickness are less than about 20 Angstroms.  
     
     
         5 . The memory circuit of  claim 1  wherein the first dopant concentration is at least 50% greater than the second dopant concentration.  
     
     
         6 . The memory circuit of  claim 1  wherein the first gate electrode and the second gate electrode are doped with one or more N-type impurities.  
     
     
         7 . The memory circuit of  claim 1  wherein the first gate electrode and the second gate electrode are doped with one or more P-type impurities.  
     
     
         8 . A DRAM circuit module comprising: 
 a capacitance device for data storage;    a pass gate device for selectively enabling the capacitance device to be electrically charged, wherein the pass gate device comprises: 
 a first gate dielectric layer, having a first physical gate dielectric thickness, formed on a substrate;  
 a first gate electrode, having a first dopant concentration, formed atop the first gate dielectric layer;  
   a peripheral logical device for operating with the pass gate device, wherein the peripheral logical device comprises: 
 a second gate dielectric layer, having a second physical gate dielectric thickness, formed on the substrate;  
 a second gate electrode, having a second dopant concentration, formed atop the second gate dielectric layer,  
   wherein the first physical gate dielectric thickness is substantially the same as the second physical gate dielectric thickness, and the second dopant concentration is made substantially greater than the first dopant concentration by at least one predetermined doping process after the pass gate device has undergone a prior doping process with the peripheral device.    
     
     
         9 . The DRAM circuit module of  claim 8  wherein the pass gate device has a first electrical gate dielectric thickness substantially greater than a second electrical gate dielectric thickness of the peripheral logic device.  
     
     
         10 . The DRAM circuit module of  claim 8  wherein the first physical gate dielectric thickness and the second physical gate dielectric thickness are less than 20 Angstroms.  
     
     
         11 . The DRAM circuit module of  claim 10  wherein the second dopant concentration is at least 50% greater than the first dopant concentration.  
     
     
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