Apparatus for providing clock signals at different locations with minimal clock skew

Abstract

A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desirable phase relationships, such as quadrature signals. The phase shift ring oscillator includes an odd number of amplifier stages. Each amplifier stage includes a phase shift network and an amplifier network. CMOS components used in the phase shift and amplifier networks provide voltage controlled variable phase shift and low gain, wide bandwidth, and low output impedance.

1 . A tapped phase shift ring oscillator for generating a plurality of phase shifted clock signals, comprising: 
 an odd number of amplifier stages each including a voltage variable resistance for providing, in combination, a phase shift of 180 degrees to a received signal; and    at least one clock line tapped to an output of at least one of the odd number of amplifier stages for receiving a phase shifted clock signal from the at least one of the odd number of amplifier stages.    
   
   
       2 . The tapped phase shift ring oscillator of  claim 1 , wherein the voltage variable resistance is comprised of an NMOS transistor.  
   
   
       3 . The tapped phase shift ring oscillator of  claim 2 , wherein each of the odd number of amplifier stages includes a capacitor having a first terminal connected to receive an input signal and a second terminal connected to the NMOS transistor.  
   
   
       4 . The tapped phase shift ring oscillator of  claim 3 , wherein the NMOS transistor comprises: 
 a drain connected to the second terminal of the capacitor;    a gate connect to a resistance-changing voltage; and    a source connected to a gate bias supply voltage.    
   
   
       5 . The tapped phase shift ring oscillator of  claim 1 , wherein each of the odd number of amplifier stages is configured to shift a received input signal by an equivalent amount.  
   
   
       6 . The tapped phase shift ring oscillator of  claim 1 , wherein at least one of the odd number of amplifier stages is configured to shift a received input signal by different amount.  
   
   
       7 . The tapped phase shift ring oscillator of  claim 1 , wherein at least one clock line comprises a corresponding odd number of clock lines respectively tapped to the outputs of the odd number of amplifier stages.  
   
   
       8 . The tapped phase shift ring oscillator of  claim 1 , wherein each of the odd number of amplifier stages comprises an amplifier network coupled to the voltage variable resistance.  
   
   
       9 . The tapped phase shift ring oscillator of  claim 8 , wherein the amplifier network, comprises: 
 an NMOS transistor, comprising a gate connected to the voltage variable resistance, a grounded source, and a drain;    a PMOS transistor, comprising a PMOS drain connected to a pull-up voltage, a PMOS gate connected to the drain of the NMOS transistor, and a PMOS source connected to the PMOS gate and the drain of the NMOS transistor; and    an output taken from a connection of the NMOS drain, the PMOS source and the PMOS gate.    
   
   
       10 . The tapped phase shift ring oscillator of  claim 1 , wherein a first voltage adjusts a resistance of one of the odd number of amplifier stages and a different second voltage adjusts a second different resistance of another one of the odd number of amplifier stages.