Single transistor RAM cell and method of manufacture

Abstract

A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

1 - 21 . (canceled)  
   
   
       22 . A single transistor planar RAM device comprising: 
 a pass transistor structure and a storage capacitor structure formed over a silicon substrate and disposed is spaced apart relationship to form a spaced distance overlying a first doped region;    wherein sidewall spacer material is disposed adjacent either side of the pass transistor structure partially covering a second doped region and fully covering the first doped region.    
   
   
       23 . The single transistor planar RAM device of  claim 22 , wherein the first doped region comprises a lower dopant concentration compared to the second doped region.  
   
   
       24 . The single transistor planar RAM device of  claim 22 , wherein the first doped region is doped to a level of between about 10 12  and 10 14  dopant atoms/cm 2  and the second doped region comprises a relatively higher doped region of greater than about 10 15  dopant atoms/cm 2 .  
   
   
       25 . The single transistor planar RAM device of  claim 23 , wherein the storage capacitor structure is disposed at least partially overlying a shallow trench isolation structure.  
   
   
       26 . The single transistor planar RAM device of  claim 23 , further comprising salicide portions formed over a portion of the second doped region, the pass transistor structure, and the storage capacitor structure.  
   
   
       27 . The single transistor planar RAM device of  claim 23 , wherein the pass transistor structure and the storage capacitor structure comprise a dielectric gate layer selected from the group consisting of SiO 2 , nitrided SiO 2 , and oxide/nitride.  
   
   
       28 . The single transistor planar RAM device of  claim 23 , wherein the pass transistor structure and the storage capacitor structure comprise a dielectric gate layer comprising material selected from the group consisting of Ta 2 O 5 , TiO 2 , HfO 2 , Y 2 O 3 , La 2 O 5 , ZrO 2 , BST, and PZT.  
   
   
       29 . The single transistor planar RAM device of  claim 23 , wherein the pass transistor structure and the storage capacitor structure comprise a memory cell formed over an N doped well region formed in a P doped silicon substrate.  
   
   
       30 . The single transistor planar RAM device of  claim 23 , wherein the first and second doped regions respectively comprise P− and P+ doped regions.  
   
   
       31 . The single transistor planar RAM device of  claim 23 , wherein the pass transistor structure and the storage capacitor structure comprise P doped polysilicon electrode portions.  
   
   
       32 . The single transistor planar RAM device of  claim 23 , wherein the spacer dielectric material comprises one or more layers selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.