Method for selectively stressing MOSFETs to improve charge carrier mobility

Abstract

A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

1 - 30 . (canceled)  
   
   
       31 . A MOSFET device pair with improved charge mobility comprising: 
 a first gate with a first semiconductor conductive type and a second gate with a second semiconductor conductive type overlying a substrate:    a first strained layer with a first type of stress overlying said first gate; and,    a second strained layer with a second type of stress overlying said second gate.    
   
   
       32 . The MOSFET device pair of  claim 31 , wherein the first and second gates comprise a respective N semiconductor conductive type and P semiconductor conductive type with a respective overlying tensile stress type first strained layer and compressive stress type second strained layer.  
   
   
       33 . The MOSFET device pair of  claim 31 , further comprising an oxide layer interposed between the first and second strained layers and the respective first and second gates.  
   
   
       34 . The MOSFET device pair of  claim 31 , wherein the first and second gates further comprise recrystallized polysilicon.  
   
   
       35 . The MOSFET device pair of  claim 31 , wherein the first and second strained layers comprise a nitride.  
   
   
       36 . The MOSFET device pair of  claim 31 , wherein the first and second strained layers are selected from the group consisting of silicon nitride and silicon oxynitride.  
   
   
       37 . The MOSFET device pair of  claim 31 , further comprising a strained channel region in the semiconductor substrate underlying the respective first and second gates comprising a strain transferred from at least one of the respective first and second gates and the first and second strained layers.  
   
   
       38 . The MOSFET device pair of  claim 31 , wherein the wherein the first and second strained layers comprise a stress level up to about 2 GPa.  
   
   
       39 . The MOSFET device pair of  claim 31 , wherein the first and second strained layers are formed at a thickness from about 50 Angstroms to about 1000 Angstroms.  
   
   
       40 . Strained channel MOSFET devices with improved charge mobility comprising: 
 a semiconductor substrate comprising N type and P type conductivity polysilicon gate electrodes;    a first strained dielectric layer having primarily a tensile stress overlying the N type conductivity gate electrodes and a second strained dielectric layer having primarily a compressive stress overlying the P type conductivity gate electrodes; and,    strained channel regions in the semiconductor substrate underlying the respective polysilicon gate electrodes comprising a strain transferred from at least one of the respective polysilicon gate electrodes and the respective first and second strained layers.    
   
   
       41 . The strained channel MOSFET devices of  claim 40 , further comprising an oxide layer interposed between the respective polysilicon gate electrodes and the respective first and second strained dielectric layers.  
   
   
       42 . The strained channel MOSFET devices of  claim 40 , wherein the N type and P type conductivity polysilicon gate electrodes comprise recrystallized polysilicon.  
   
   
       43 . The strained channel MOSFET devices of  claim 40 , wherein the first and second strained dielectric layers are selected from the group consisting of silicon nitride and silicon oxynitride.  
   
   
       44 - 49 . (canceled)