Processes for turning a SRAM cell off and processess for writing a SRAM cell

Abstract

A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.

1 - 37 . (canceled)  
   
   
       38 . A process for turning a SRAM cell OFF comprising increasing a voltage applied to a switch in the SRAM cell above a threshold voltage for that switch.  
   
   
       39 . The process of  claim 38 , wherein the act of turning a SRAM cell OFF comprises turning a row of SRAM cells OFF.  
   
   
       40 . The process of  claim 38 , wherein the SRAM cell comprises a first transistor and a second transistor, wherein the switch comprises the second transistor and wherein the second transistor comprises an ultrathin NMOS transistor having a gate, a source, a drain and a threshold voltage, the source being coupled to a row address line and the drain being coupled to a column address line and wherein the act of turning a SRAM cell OFF comprises raising a voltage coupled to the row address line above the threshold and turning a row of SRAM cells coupled to that row address line OFF.  
   
   
       41 . The process of  claim 38 , wherein the act of turning a SRAM cell OFF comprises turning OFF all of the transistors in that cell.  
   
   
       42 . The process of  claim 38 , wherein the first transistor comprises an ultrathin PMOS transistor having a gate, a source and a drain and the switch comprises the second transistor, the second transistor comprising an ultrathin NMOS transistor having a gate, a source and a drain, the NMOS transistor source being coupled to a row address line and the NMOS transistor drain being coupled to a column address line and wherein the act of turning a SRAM cell OFF comprises: 
 raising a voltage coupled to the row address line above the threshold and turning the NMOS transistor coupled to that row address line OFF; and    causing a source-drain voltage of the PMOS transistor to become less than a threshold voltage for the PMOS transistor in response to the NMOS transistor turning OFF.    
   
   
       43 . The process of  claim 38 , wherein the SRAM cell is coupled to a row address line and wherein the act of turning a SRAM cell OFF comprises raising a voltage coupled to the row address line from about zero volts to about 0.7 volts or less.  
   
   
       44 . The process of  claim 38 , wherein the act of turning a SRAM cell OFF comprises turning OFF both of the two transistors in that cell.  
   
   
       45 . A process for writing a SRAM cell comprising two switches, where one of the two switches is coupled to a row address line and a column address line, to an ON state, comprising modifying a voltage coupled to the row address line to cause a voltage applied to a control electrode of the one switch to exceed a threshold voltage for that switch.  
   
   
       46 . The process of  claim 45 , further comprising modifying voltages coupled to column address lines of SRAM cells that are not to be written to the ON state to prevent the row address line voltage modification from turning ON switches in the SRAM cells that are not to be written to the ON state.  
   
   
       47 . The process of  claim 46 , wherein modifying voltages coupled to column address lines comprises raising the voltages coupled to the address lines of SRAM cells that are not to be written to the ON state.  
   
   
       48 . The process of  claim 45 , wherein at least one of the two switches comprises a NMOS FET having a gate, drain, source and threshold voltage V TN , wherein the source is coupled to the row address line and the drain is coupled to the column address line, wherein modifying a voltage coupled to the row address line comprises reducing the voltage coupled to the row address line below ground to cause a voltage applied to the gate to exceed the threshold voltage V TN .  
   
   
       49 . The process of  claim 45 , further comprising, prior to modifying a voltage, writing a row of SRAM cells coupled to the row address line to the OFF state.  
   
   
       50 - 55 . (canceled)