Novel CMOS device

Abstract

A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

1 . A semiconductor device comprising: 
 at least one NMOS device;    at least one PMOS device adjacent the at least one NMOS device;    a first stress layer overlying the at least one PMOS device; the first stress layer having a first stress characteristic; and    a second stress layer overlying the at least one NMOS device; the second stress layer having a second stress characteristic;    whereby the first stress characteristic is tensile and the second stress characteristic is tensile; or the first stress characteristic is compressive and the second stress characteristic.    
   
   
       2 . The device of  claim 1 , wherein the structure is a silicon substrate or a silicon-germanium substrate.  
   
   
       3 . The device of  claim 1 , wherein the structure is a silicon substrate.  
   
   
       4 . The device of  claim 1 , wherein: 
 the first stress layer is a rapid thermal CVD layer and the second stress layer is a rapid thermal CVD layer; or    the first stress layer is a PECVD layer and the second stress layer is a rapid thermal CVD layer.    
   
   
       5 . The device of  claim 1 , wherein the first stress layer and the second stress layer are each comprised of SiON.  
   
   
       6 . The device of  claim 1 , wherein the NMOS device and the PMOS device each further includes a gate oxide layer having a thickness of less than about 17 Å.  
   
   
       7 . The device of  claim 1 , wherein the NMOS device and the PMOS device each further includes a device channel having a design width of less than about 0.5 μm.  
   
   
       8 . The device of  claim 1 , wherein the semiconductor device has an operation voltage design of less than about 1.2 volts.  
   
   
       9 . The device of  claim 1 , whereby the semiconductor device has improved mobility of holes and electrons.  
   
   
       10 . The device of  claim 1 , wherein the semiconductor device further includes an isolation structure between the at least one NMOS device and the at least one PMOS device.  
   
   
       11 . The device of  claim 1 , wherein the semiconductor device further includes an STI structure between the at least one NMOS device and the at least one PMOS device.  
   
   
       12 . The device of  claim 1 , wherein the at least one NMOS device further includes sidewall spacers and the at least one PMOS device further includes sidewall spacers.  
   
   
       13 . The device of  claim 1 , wherein the first stress layer and the second stress layer  50 ′ are each comprised of Si-rich nitride, SiON or SiN.  
   
   
       14 . A semiconductor device comprising: 
 at least one NMOS device;    at least one PMOS device adjacent the at least one NMOS device;    a first stress layer overlying the at least one PMOS device; the first stress layer having a first stress characteristic; and    a second stress layer overlying the at least one NMOS device; the second stress layer having a second stress characteristic; whereby: 
 (1) the first stress characteristic is tensile and the second stress characteristic is tensile, or the first stress characteristic is compressive and the second stress characteristic; and  
 (2) the first stress layer is a rapid thermal CVD layer and the second stress layer is a rapid thermal CVD layer; or the first stress layer is a PECVD layer and the second stress layer is a rapid thermal CVD layer.  
   
   
   
       15 . The device of  claim 14 , wherein the structure is a silicon substrate or a silicon-germanium substrate.  
   
   
       16 . The device of  claim 14 , wherein the structure is a silicon substrate.  
   
   
       17 . The device of  claim 14 , wherein the first stress layer and the second stress layer are each comprised of SiON.  
   
   
       18 . The device of  claim 14 , wherein the NMOS device and the PMOS device each further includes a gate oxide layer having a thickness of less than about 17 Å.  
   
   
       19 . The device of  claim 14 , wherein the NMOS device and the PMOS device each further includes a device channel having a design width of less than about 0.5 μm.  
   
   
       20 . The device of  claim 14 , wherein the semiconductor device has an operation voltage design of less than about 1.2 volts.  
   
   
       21 . The device of  claim 14 , whereby the semiconductor device has improved mobility f holes and electrons.  
   
   
       22 . The device of  claim 14 , wherein the semiconductor device further includes an isolation structure between the at least one NMOS device and the at least one PMOS device.  
   
   
       23 . The device of  claim 14 , wherein the semiconductor device further includes an STI structure between the at least one NMOS device and the at least one PMOS device.  
   
   
       24 . The device of  claim 14 , wherein the at least one NMOS device further includes sidewall spacers and the at least one PMOS device further includes sidewall spacers.  
   
   
       25 . The device of  claim 14 , wherein the first stress layer and the second stress layer are each comprised of Si-rich nitride, SiON or SiN.