Semiconductor wafer with an epitaxially deposited layer, and process for producing the semiconductor wafer

Abstract

A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n ++ or p ++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n + or p + to the level n ++ or p ++ , and an epitaxial layer is then deposited on this layer.

1 . A semiconductor wafer comprising a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, an epitaxial layer on the front surface, and an n ++  or p ++  doped layer with a lower resistivity than the substrate wafer, positioned below the epitaxial layer and extending into the substrate wafer.  
   
   
       2 . The semiconductor wafer of  claim 1 , wherein the n ++  or p ++  doped layer is substantially devoid of dislocations.  
   
   
       3 . The semiconductor wafer of  claim 1 , wherein the thickness of the substrate wafer is less than 120 μm.  
   
   
       4 . The semiconductor wafer of  claim 1 , wherein electronic components are integrated in the epitaxially deposited layer.  
   
   
       5 . The semiconductor wafer of  claim 1 , wherein the thickness of the semiconductor wafer following a process for fabricating electronic components is less than 120 μm.  
   
   
       6 . An electronic component, such as a power MOSFET, a power IC or an IGBT, fabricated from the semiconductor wafer of  claim 1 .  
   
   
       7 . A process for producing an epitaxially coated semiconductor wafer with low resistivity below the epitaxial layer, comprising 
 providing a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type and having a front surface and a back surface,    forming a layer on the front surface of the substrate wafer by introducing additional dopant atoms of the n type or p type into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in this layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n +  or p +  to the level n ++  or p ++ , and depositing an epitaxial layer is deposited on the front surface of the substrate wafer.    
   
   
       8 . The process of  claim 7 , wherein the dopants are introduced into the substrate wafer by diffusion.  
   
   
       9 . The process of  claim 7 , wherein the dopants are introduced into the substrate wafer by implantation.  
   
   
       10 . The process of  claim 7 , wherein the back surface of the substrate wafer is ground.  
   
   
       11 . The process of  claim 7 , wherein the thickness of the substrate wafer is reduced following a process for fabricating electronic components.  
   
   
       12 . The process of  claim 11 , wherein the back surface of the substrate wafer is ground.  
   
   
       13 . The process of  claim 7 , further comprising fabricating a plurality of electronic components on the wafer, and removing them from the back surface of the wafer sufficient thickness to remove substantially all of the n +  or p +  doped single crystal silicon.