Integration of silicon carbide into DRAM cell to improve retention characteristics

Abstract

A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.

1 . A semiconductor device comprising: 
 a semiconductor substrate, the substrate having a surface;    a trench formed in the surface of the semiconductor substrate, the trench having a sidewall;    a first doped region including carbon provided in a sidewall of the trench, the first doped region extending a first depth into the semiconductor substrate; and    a second doped region including germanium provided in a portion of the first doped region, the second doped region extending a second depth into the semiconductor substrate, the second depth being less than the first depth.    
   
   
       2 . A semiconductor device comprising: 
 a semiconductor substrate, the substrate having a surface;    a trench provided in the surface of the semiconductor substrate, the trench having a sidewall;    a first region in the sidewall of the trench including silicon carbide, the first region provided at a predetermined depth below the surface of the semiconductor substrate; and    a second region in the sidewall of the trench including silicon germanium carbide, the second region provided between the surface of the semiconductor substrate and the first region.    
   
   
       3 . A DRAM memory cell, comprising: 
 a semiconductor substrate, including a trench formed therein and a buried plate region;    at least a first doped region and a second doped region provided on a sidewall of the trench spaced from the buried plate region in the substrate, the first doped region extending a first depth into the semiconductor substrate, and the second doped region extending a second depth into the semiconductor substrate, the second depth being less than the first depth, 
 wherein the first doped region includes carbon and the second doped region includes germanium;  
   a dielectric layer formed on the bottom and sidewall of the trench;    at least one conductive layer deposited in the trench and on the dielectric layer, the at least one conductive layer covering the dielectric layer; and    a transistor formed on a surface of the semiconductor substrate.    
   
   
       4 . The DRAM memory cell according to  claim 3 , wherein the trench has a depth of about 7 μm to about 8 μm.  
   
   
       5 . The DRAM memory cell according to  claim 3 , wherein the trench width varies from about 180 nm to about 220 nm.  
   
   
       6 . The DRAM memory cell according to  claim 3 , wherein the first doped region and the second doped region are formed by ion implantation.  
   
   
       7 . The DRAM memory cell according to  claim 3 , wherein the first doped region includes silicon carbide.  
   
   
       8 . The DRAM memory cell according to  claim 3 , wherein the second doped region includes silicon germanium carbide.  
   
   
       9 . The DRAM memory cell according to  claim 3 , wherein the first doped region contains an implanted concentration of about 8×10 15  cm −2  to about 3×10 16  cm −2 .  
   
   
       10 . The DRAM memory cell according to  claim 3 , wherein the second doped region contains an implanted concentration of about 1×10 15  cm −2  to about 5×10 15  cm −2 .  
   
   
       11 . The DRAM memory cell according to  claim 3 , wherein the second doped region extends from about 100 to about 150 nm into the substrate in a direction perpendicular to the surface of the semiconductor substrate.  
   
   
       12 . The DRAM memory cell according to  claim 3 , wherein the dielectric layer is composed of a material including an oxide or a nitride.  
   
   
       13 . The DRAM memory cell according to  claim 3 , wherein a thickness of a top portion of the dielectric layer is thicker than a thickness of another portion of the dielectric layer.  
   
   
       14 . The DRAM memory cell according to  claim 3 , wherein a portion of the dielectric layer is about 40 nm to about 60 nm thick in a direction perpendicular to a sidewall of the trench.  
   
   
       15 . The DRAM memory cell according to  claim 3 , further comprising a transistor, the transistor including a gate oxide layer formed on a surface of the substrate, a gate formed on the gate oxide layer, and at least first and second impurity regions formed in a surface of the substrate, the first impurity region being spaced from the second impurity region and being coupled with the second doped region.  
   
   
       16 .- 31 . (canceled)